Pavel I Smetana

US Patent:

6626188, Sep 30, 2003

Filed:

Jun 28, 2001

Appl. No.:

09/894499

Inventors:

John A. Fitzsimmons - Poughkeepsie NY
Thomas H. Ivers - Hopewell Junction NY
Pavel Smetana - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C25F 500

US Classification:

134 11, 134 2, 134 21, 134 221, 134 2218, 134 26, 134 30, 216 63, 216 64, 15634524, 15634533, 15634534, 15634537, 15634548, 438905

Abstract:

The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to a method for cleaning and preconditioning a dome in a chemical vapor deposition system. During cleaning, the direction of flow of cooling water through an induction coil in the dome is reversed. During preconditioning, the direction of cooling water flow is preferably reversed again, such that it is the same direction as during deposition. The preconditioning portion of the method comprises introducing a hydrogen gas into the CVD chamber, and then introducing a mixture of hydrogen gas and nitrogen gas into the chamber.

US Patent:

7372689, May 13, 2008

Filed:

Apr 4, 2005

Appl. No.:

10/907508

Inventors:

Scott M. Hargash - Esopus NY, US
Pavel Smetana - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02N 13/00

US Classification:

361234, 20429811

Abstract:

An apparatus (and method for operating the same) which allows tightly coupling the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The method comprises (a) providing (i) a process chamber and (ii) an electrostatic chuck in the process chamber; (b) placing a guard wafer on the electrostatic chuck via a top surface of the electrostatic chuck; and (c) forming a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber, wherein the particle restraining layer has a thickness in a first direction of at least 500 Å, wherein the first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and an inner surface of the process chamber, and wherein the guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.

US Patent:

7489494, Feb 10, 2009

Filed:

Apr 11, 2008

Appl. No.:

12/101231

Inventors:

Scott M. Hargash - Esopus NY, US
Pavel Smetana - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02N 13/00

US Classification:

361234, 20429811

Abstract:

An apparatus which allows tightly coupling of the device wafer to the electrostatic chuck of the process chamber after the process chamber is conditioned. The apparatus includes (a) a process chamber; (b) a chuck in the process chamber; (c) a guard wafer placed on and in direct physical contact with the chuck; and (d) a particle restraining layer on essentially all surfaces that are exposed to the ambient inside the process chamber. The particle restraining layer has a thickness in a first direction of at least 500 nm. The first direction is essentially perpendicular to an interfacing surface between the particle restraining layer and the chuck. The guard wafer comprises a material selected from the group consisting of a metal and a semiconductor oxide.

US Patent:

20040137745, Jul 15, 2004

Filed:

Jan 10, 2003

Appl. No.:

10/341275

Inventors:

Thomas Houghton - Marlboro NY, US
Bradley Jones - Pleasant Valley NY, US
Pavel Smetana - Poughkeepsie NY, US
Horatio Wildman - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/302
H01L021/461

US Classification:

438/706000

Abstract:

A method and apparatus for removing a deposited layer on a bottom surface of a substrate, the deposited layer proximate to an edge of the substrate. The method comprises: providing a chuck for supporting the bottom surface of the substrate, an peripheral portion of the bottom surface proximate to the edge extending past a periphery of the chuck; positioning a shield spaced away from and over a top surface of the substrate, a bottom surface of the shield opposite a top surface of the substrate; directing a reactant containing gas to the bottom surface of the substrate proximate to the edge of the substrate; and converting the reactant gas to a reactant species, the reactant species reacting with the deposited layer in order to cause removal of the deposited layer from the substrate.

US Patent:

20050011442, Jan 20, 2005

Filed:

Jun 24, 2003

Appl. No.:

10/604058

Inventors:

Bomy Chen - Cupertino CA, US
John Fitzsimmons - Poughkeepsie NY, US
Vincent McGahay - Poughkeepsie NY, US
James Ryan - Newtown CT, US
Pavel Smetana - Poughkeepsie NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

C23C016/00
H05H001/24

US Classification:

118715000, 427345000, 427569000

Abstract:

An integrated circuit plasma processing system, apparatus and method for reclaiming material, such as a plasma precursor and potentially useful components among their byproducts, from plasma-enhanced exhaust of a plasma process chamber for subsequent reuse in the chamber. The apparatus provides a recycle feedback loop for a plasma process chamber that provides the high purity materials necessary for microelectronic applications. Since the apparatus is in-situ, no byproducts that are not already present are possible. Accordingly, the apparatus guarantees purity of the recycled material. In addition to cost savings, the invention provides an environmentally friendly plasma process chamber and apparatus with very little production of waste.

US Patent:

20100029082, Feb 4, 2010

Filed:

Aug 4, 2008

Appl. No.:

12/185339

Inventors:

Daewon Yang - Hopewell Junction NY, US
Kangguo Cheng - Guilderland NY, US
Pavel Smetana - Poughkeepsie NY, US
Richard S. Wise - Newburgh NY, US
Keith Kwong Hon Wong - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/311
C23C 16/00

US Classification:

438696, 118723 R, 257E2124

Abstract:

Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

US Patent:

20120190203, Jul 26, 2012

Filed:

Mar 30, 2012

Appl. No.:

13/434934

Inventors:

Daewon Yang - Hopewell Junction NY, US
Kangguo Cheng - Hopewell Junction NY, US
Pavel Smetana - Hopewell Junction NY, US
Richard S. Wise - Hopewell Junction NY, US
Keith Kwong Hon Wong - Hopewell Junction NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/311

US Classification:

438700, 438694, 257E21249

Abstract:

Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

US Patent:

51594293, Oct 27, 1992

Filed:

May 11, 1992

Appl. No.:

7/884318

Inventors:

Robert E. Bendernagel - Carmel NY
Victor J. Silvestri - Hopewell Junction NY
Pavel Smetana - Poughkeepsie NY
Thomas H. Strudwick - Wappingers Falls NY
William H. White - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2704

US Classification:

357 50

Abstract:

A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.