Peng P Wu

US Patent:

8438568, May 7, 2013

Filed:

Feb 24, 2010

Appl. No.:

12/711352

Inventors:

Mark E. Giampapa - Irvington NY, US
Thomas M. Gooding - Rochester MN, US
Raul E. Silvera - Ontario, CA
Kai-Ting Amy Wang - Ontario, CA
Peng Wu - Rochester NY, US
Xiaotong Zhuang - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46
G06F 7/00
G06F 13/00

US Classification:

718100, 718101, 712220, 711100, 711118, 711147

Abstract:

In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.

US Patent:

20190294444, Sep 26, 2019

Filed:

Jun 12, 2019

Appl. No.:

16/439210

Inventors:

- Armonk NY, US
Jose Moreira - Irvington NY, US
Jessica H. Tseng - Fremont CA, US
Peng Wu - Rochester NY, US

International Classification:

G06F 9/38
G06F 8/41
G06F 15/80

Abstract:

There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running Single Program Multiple Data code on a Single Instruction Multiple Data machine. The machine runs an instruction stream over input data streams and machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation and updates the lane-PC of each active lane according to targets of the branch operation. An instruction of the instruction stream includes a barrier indicating a convergence point for all lanes to join. In response to a lane reaching a barrier: evaluating whether all lane-PCs are set to a same thread-PC; and if the lane-PCs are not set to the same thread-PC, selecting an active lane from the plurality of lanes; otherwise, incrementing the lane-PCs of all the lanes, and then selecting an active lane from the plurality of lanes.

US Patent:

20180232239, Aug 16, 2018

Filed:

Feb 7, 2018

Appl. No.:

15/890548

Inventors:

- Armonk NY, US
Jose Moreira - Irvington NY, US
Jessica H. Tseng - Fremont CA, US
Peng Wu - Rochester NY, US

International Classification:

G06F 9/38
G06F 15/80
G06F 8/41
G06F 9/30
G06F 9/32

Abstract:

There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running SPMD (Single Program Multiple Data) code on SIMD (Single Instruction Multiple Data) machine. The machine runs an instruction stream over input data streams. The machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation. The machine updates the lane-PC of each active lane according to targets of the branch operation. The machine selects an active lane and activates only lanes whose lane-PCs match the thread-PC. The machine decrements the lane depth counters of the selected active lanes and updates the lane-PC of each active lane upon the instruction stream reaching a first instruction. The machine assigns the lane-PC of a lane with a largest lane depth counter value to the thread-PC and activates all lanes whose lane-PCs match the thread-PC.

US Patent:

20160147536, May 26, 2016

Filed:

Nov 24, 2014

Appl. No.:

14/552145

Inventors:

- Armonk NY, US
Jose E. Moreira - Irvington NY, US
Mauricio J. Serrano - Bronx NY, US
Ilie G. Tanase - Somers NY, US
Jessica H. Tseng - Fremont CA, US
Peng Wu - Rochester NY, US

International Classification:

G06F 9/30

Abstract:

Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.

US Patent:

20160147537, May 26, 2016

Filed:

Sep 30, 2015

Appl. No.:

14/870367

Inventors:

- Armonk NY, US
Jose E. Moreira - Irvington NY, US
Mauricio J. Serrano - Bronx NY, US
Ilie G. Tanase - Somers NY, US
Jessica H. Tseng - Fremont CA, US
Peng Wu - Rochester NY, US

International Classification:

G06F 9/30

Abstract:

Techniques for switching between two (thread and lane) modes of execution in a dual execution mode processor are provided. In one aspect, a method for executing a single instruction stream having alternating serial regions and parallel regions in a same processor is provided. The method includes the steps of: creating a processor architecture having, for each architected thread of the single instruction stream, one set of thread registers, and N sets of lane registers across N lanes; executing instructions in the serial regions of the single instruction stream in a thread mode against the thread registers; executing instructions in the parallel regions of the single instruction stream in a lane mode against the lane registers; and transitioning execution of the single instruction stream from the thread mode to the lane mode or from the lane mode to the thread mode.

US Patent:

20160062771, Mar 3, 2016

Filed:

Aug 26, 2014

Appl. No.:

14/468904

Inventors:

- Armonk NY, US
Jose Moreira - Irvington NY, US
Jessica H. Tseng - Fremont CA, US
Peng Wu - Rochester NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/38
G06F 9/45

Abstract:

There are provided a system, a method and a computer program product for selecting an active data stream (a lane) while running SPMD (Single Program Multiple Data) code on SIMD (Single Instruction Multiple Data) machine. The machine runs an instruction stream over input data streams. The machine increments lane depth counters of all active lanes upon the thread-PC reaching a branch operation. The machine updates the lane-PC of each active lane according to targets of the branch operation. The machine selects an active lane and activates only lanes whose lane-PCs match the thread-PC. The machine decrements the lane depth counters of the selected active lanes and updates the lane-PC of each active lane upon the instruction stream reaching a first instruction. The machine assigns the lane-PC of a lane with a largest lane depth counter value to the thread-PC and activates all lanes whose lane-PCs match the thread-PC.