Peng Zhang

US Patent:

20230099107, Mar 30, 2023

Filed:

Sep 27, 2021

Appl. No.:

17/485949

Inventors:

- Addison TX, US
Peng ZHANG - San Jose CA, US

International Classification:

H01L 27/11551
H01L 27/11578
H01L 27/11529
H01L 27/11573

Abstract:

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a semiconductor material layer, an inter-tier dielectric layer, and a second alternating stack of second insulating layers and second electrically conductive layers located over the inter-tier dielectric layer. A memory opening vertically extends through the second alternating stack, the inter-tier dielectric layer, and the first alternating stack. A memory opening fill structure is located in the memory opening, and includes a first vertical semiconductor channel, a second vertical semiconductor channel, and an inter-tier doped region located between the first and the second semiconductor channel, and providing a first p-n junction with the first vertical semiconductor channel and providing a second p-n junction with the second vertical semiconductor channel.

US Patent:

20210408024, Dec 30, 2021

Filed:

Jun 30, 2020

Appl. No.:

16/916186

Inventors:

- Addison TX, US
Yanli Zhang - San Jose CA, US
Peng Zhang - San Jose CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

H01L 27/11556
G11C 5/02
G11C 5/06
H01L 29/06
H01L 27/11582

Abstract:

A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

US Patent:

20210159169, May 27, 2021

Filed:

Nov 27, 2019

Appl. No.:

16/697560

Inventors:

- ADDISON TX, US
Zhiping ZHANG - Milpitas CA, US
Peng ZHANG - Fremont CA, US
Deepanshu DUTTA - Fremont CA, US

International Classification:

H01L 23/522
H01L 23/528
G11C 5/06
G11C 16/16
H01L 27/11519
H01L 27/11524
H01L 27/11556
H01L 27/11565
H01L 27/1157
H01L 27/11582

Abstract:

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.

US Patent:

20210134372, May 6, 2021

Filed:

Nov 6, 2019

Appl. No.:

16/676023

Inventors:

- Addison TX, US
Muhammad Masuduzzaman - San Jose CA, US
Peng Zhang - San Jose CA, US
Dengtao Zhao - San Jose CA, US
Deepanshu Dutta - San Jose CA, US

Assignee:

SanDisk Technologies LLC - Addison TX

International Classification:

G11C 16/26
G11C 16/10
G11C 16/34
G06F 3/06

Abstract:

A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

US Patent:

20200234778, Jul 23, 2020

Filed:

Apr 3, 2020

Appl. No.:

16/840156

Inventors:

- Addison TX, US
Peng Zhang - San Jose CA, US
Nan Lu - San Jose CA, US
Deepanshu Dutta - Fremont CA, US

Assignee:

SANDISK TECHNOLOGIES LLC - Addison TX

International Classification:

G11C 16/34
G11C 16/12
G11C 8/08
G11C 11/408
G11C 16/04

Abstract:

Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

US Patent:

20190378580, Dec 12, 2019

Filed:

Jun 7, 2018

Appl. No.:

16/002825

Inventors:

- Addison TX, US
Peng Zhang - San Jose CA, US
Nan Lu - San Jose CA, US
Deepanshu Dutta - Fremont CA, US

Assignee:

SANDISK TECHNOLOGIES LLC - Addison TX

International Classification:

G11C 16/34
G11C 16/12
G11C 11/408
G11C 8/08
G11C 16/04

Abstract:

Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

US Patent:

20190378581, Dec 12, 2019

Filed:

Jun 7, 2018

Appl. No.:

16/002836

Inventors:

- Addison TX, US
Peng Zhang - San Jose CA, US
Nan Lu - San Jose CA, US
Deepanshu Dutta - Fremont CA, US

Assignee:

SANDISK TECHNOLOGIES LLC - Addison TX

International Classification:

G11C 16/34
G11C 16/10
G11C 16/08
G11C 16/04
H01L 27/11582
H01L 27/1157

Abstract:

Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

US Patent:

20190214395, Jul 11, 2019

Filed:

Jan 9, 2018

Appl. No.:

15/865892

Inventors:

- Plano TX, US
Peng Zhang - Fremont CA, US
Johann Alsmeier - San Jose CA, US
Yingda Dong - San Jose CA, US

International Classification:

H01L 27/1157
H01L 27/11578
G11C 16/04
G11C 16/10

Abstract:

A method of operating a three-dimensional memory device includes applying a target string bias voltage to a selected drain select gate electrode which partially surrounds a row of memory stack structures that directly contact a drain select isolation structure, and applying a neighboring string bias voltage that has a greater magnitude than the target string bias voltage to an unselected drain select gate electrode that contacts the drain select level isolation structure.