Peter R Harper

US Patent:

20130175684, Jul 11, 2013

Filed:

Jan 5, 2012

Appl. No.:

13/343880

Inventors:

Kenneth R. Rhyner - Rockwall TX, US
Peter Harper - Gilroy CA, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H05K 1/02
H01L 23/488

US Classification:

257738, 174261, 257E23023

Abstract:

A ball grid array (BGA) includes a plurality of metal balls adapted for connection between an electrical circuit and a substrate. A first portion of the BGA contains a first group of the metal balls arranged according to a first pitch. A second portion of the BGA contains a second group of metal the balls arranged according to a second pitch that is less than the first pitch, to provide increased metal contact area and correspondingly enhanced thermal transfer capability.

US Patent:

20130295722, Nov 7, 2013

Filed:

Jul 11, 2013

Appl. No.:

13/939804

Inventors:

Peter R. Harper - Morgan Hill CA, US

International Classification:

H01L 23/00

US Classification:

438121

Abstract:

A method for forming an integrated circuit package is disclosed. A flex circuit is form by forming a direct connect pad on a first side of a dielectric layer. After forming the direct connect pad, an opening from a second side of the dielectric layer is formed to expose the direct connect pad. A blind via is formed within the opening in the dielectric layer. A first conductor is formed within the opening. A bond pad of a semiconductor die is electrically coupled with the direct connect pad using a second conductor, wherein the bond pad and the second conductor directly overlie the direct connect pad.

US Patent:

20140077355, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/617915

Inventors:

Peter R. Harper - Gilroy CA, US
Arkadii V. Samoilov - Saratoga CA, US
Don Dias - Lewisville TX, US

Assignee:

MAXIM INTEGRATED PRODUCTS, INC. - San Jose CA

International Classification:

H01L 23/498
H01L 21/56

US Classification:

257737, 438126, 257E23068, 257E21502

Abstract:

A semiconductor package device that includes an integrated circuit device package having a storage circuitry is disclosed. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to (e.g., adjacent to, in, or on) the first surface. The semiconductor package device also includes an integrated circuit device disposed over the second surface, the integrated circuit device including storage circuitry for storing sensitive data. In one or more implementations, the semiconductor package device includes a through-substrate via that furnishes an electrical connection to the integrated circuit package. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the integrated circuit device package.

US Patent:

20140077385, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/618116

Inventors:

Peter R. Harper - Gilroy CA, US

Assignee:

MAXIM INTEGRATED PRODUCTS, INC. - San Jose CA

International Classification:

H01L 23/48

US Classification:

257774, 257E23011

Abstract:

A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to the first surface. The semiconductor package device also includes a passive energy component positioned over the second surface. The passive energy component is electrically connected to one or more integrated circuits. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the passive energy component.

US Patent:

20200107435, Apr 2, 2020

Filed:

Apr 4, 2019

Appl. No.:

16/375493

Inventors:

- Cupertino CA, US
Karthik Shanmugam - Singapore, SG
Peter R. Harper - Gilroy CA, US
Tongbi Tom Jiang - Santa Clara CA, US

International Classification:

H05K 1/02
H01L 33/24
H01L 25/16
H05K 5/06
H01L 23/31
H01L 33/08
H01L 33/62

Abstract:

An optical module may be formed on a wafer. The wafer may include a substrate and one or more optical components encapsulated, at least partially, by the substrate. Each of the optical components are configured to emit or sense light. The wafer may also include one or more printed circuit board (PCB) bars encapsulated, at least partially, by the substrate allowing electrical conductivity from a first side of the substrate to a second side of the substrate. The wafer may also include at least one redistribution layer to electrically couple at least one of the optical components to at least one of the PCB bars.

US Patent:

20200107436, Apr 2, 2020

Filed:

Apr 4, 2019

Appl. No.:

16/375503

Inventors:

- Cupertino CA, US
Karthik Shanmugam - Singapore, SG
Peter R. Harper - Gilroy CA, US
Tongbi Tom Jiang - Santa Clara CA, US

International Classification:

H05K 1/02
H01L 33/24
H01L 25/16
H01L 23/31
H01L 33/08
H01L 33/62

Abstract:

A method for manufacturing an optical wafer may include coating multiple optical components with a substrate. The multiple optical components may include a light emitting component and a light detecting component, and each of the optical components may include one or more electrical connections. The method may also include depositing a redistribution layer onto at least one of the electrical connections, wherein the redistribution layer routes the electrical connection within the optical wafer to an external connection. The method may also include depositing a passivation layer over the redistribution layer and depositing a dark photoresist layer on at least the passivation layer. The photoresist layer may operatively reduce optical interference between at least one light emitting component and at least one light detecting component.

US Patent:

20150325512, Nov 12, 2015

Filed:

Jul 20, 2015

Appl. No.:

14/803612

Inventors:

- San Jose CA, US
Peter R. Harper - Gilroy CA, US
Viren Khandekar - Flower Mound TX, US
Pirooz Parvarandeh - Los Altos Hills CA, US

International Classification:

H01L 23/498
H01L 21/311
H01L 21/48
H01L 23/00
H01L 21/56

Abstract:

Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.

US Patent:

20150279799, Oct 1, 2015

Filed:

Sep 22, 2014

Appl. No.:

14/492576

Inventors:

- San Jose CA, US
Peter R. Harper - Gilroy CA, US
Sriram Muthukumar - Allen TX, US
Arkadii V. Samoilov - Saratoga CA, US

International Classification:

H01L 23/00
H01L 21/78

Abstract:

A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar.

Address:

8155 Burchell Rd, Gilroy, CA 95020

Phone:

(972)4429928

VIN:

1FAHP32N79W136344

Make:

FORD

Model:

FOCUS

Year:

2009