Peter D Holm

US Patent:

20220352879, Nov 3, 2022

Filed:

Apr 30, 2021

Appl. No.:

17/246145

Inventors:

- Dover DE, US
Peter Holm - Seattle WA, US
Steve Beccue - Frazier Park CA, US

Assignee:

Bitmain Development Inc. - Dover DE

International Classification:

H03K 5/01
H03K 17/687

Abstract:

Embodiments of the invention provide for a dynamic pulse generator which can combine both the sequential element and the pulse logic into one stage, thereby eliminating the wasted time resulting from a pulse generator' input-to-output propagation delay. The dynamic pulse generator can include a plurality of P-MOS an N-MOS transistors, a first delay element, and a second delay element.

US Patent:

20200142461, May 7, 2020

Filed:

Oct 31, 2019

Appl. No.:

16/670811

Inventors:

- San Jose CA, US
Peter Douglas HOLM - Seattle WA, US

International Classification:

G06F 1/26
G06Q 20/06

Abstract:

A multi-core processing integrated circuit (IC) chip includes a plurality of processing unit groups. Each processing unit group includes a group voltage input terminal, a group voltage ground terminal, and one or more processing units, each processing unit having a voltage input terminal and a voltage ground terminal. The plurality of processing unit groups includes a bottom-level processing unit group and a top-level processing unit group. The group voltage ground terminal of the bottom-level processing unit group is connected to a ground pin of the multi-core processing integrated circuit chip. For each processing unit group other than the bottom-level processing unit group, the group voltage ground terminal of the processing unit group is connected to the group voltage input terminal of a previous-level processing unit group within the plurality of processing unit groups. The group voltage input terminal of the top-level processing unit group is connected to a voltage power input pin of the multi-core processing integrated circuit chip.

US Patent:

20200143851, May 7, 2020

Filed:

Nov 4, 2019

Appl. No.:

16/673124

Inventors:

- San Jose CA, US
Peter Douglas HOLM - Seattle WA, US

International Classification:

G11C 7/06
G11C 7/10
G11C 7/22

Abstract:

A data storage device includes a dynamic latch circuit. The dynamic latch circuit includes a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A source terminal of the first NMOS transistor is connected to a source terminal of the first PMOS transistor to form a data input terminal. A drain terminal of the first NMOS transistor is connected to a drain terminal of the first PMOS transistor to form a latch internal node. A gate terminal of the first NMOS transistor is connected to a clock input signal. A gate terminal of the first PMOS transistor is connected to an inverse clock input signal. A gate terminal of the second NMOS transistor and a gate terminal of the second PMOS transistor are connected to the latch internal node. A drain terminal of the second NMOS transistor and a drain terminal of the second PMOS transistor are connected to form an inverted output terminal.