Peter C Jenkins

US Patent:

6954920, Oct 11, 2005

Filed:

Jun 30, 2003

Appl. No.:

10/604174

Inventors:

Peter J. Jenkins - Colchester VT, US
Raminderpal Singh - Essex Junction VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

716 13, 716 12, 716 14

Abstract:

A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.

US Patent:

7085993, Aug 1, 2006

Filed:

Jul 29, 2002

Appl. No.:

10/064582

Inventors:

Kenneth J. Goodnow - Essex VT, US
Peter J. Jenkins - Colchester VT, US
Francis A. Kampf - Jeffersonville VT, US
Jason M. Norman - South Burlington VT, US
Sebastian T. Ventrone - South Burlington VT, US

Assignee:

International Business Machine Corporation - Armonk NY

International Classification:

G06F 11/08

US Classification:

714798, 714789, 714814, 714 55, 713500, 702125

Abstract:

A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

US Patent:

7113488, Sep 26, 2006

Filed:

Apr 24, 2002

Appl. No.:

10/063456

Inventors:

Peter J. Jenkins - Colchester VT, US
Francis A. Kampf - Jeffersonville VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 12/28

US Classification:

370258

Abstract:

A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

US Patent:

7793030, Sep 7, 2010

Filed:

Oct 22, 2007

Appl. No.:

11/875974

Inventors:

Peter Joel Jenkins - Colchester VT, US
Paul Joseph Mattos - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/40

US Classification:

710307, 710313, 370276, 370433, 713320, 713323

Abstract:

A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of K lanes and each lane of the set of N lanes consisting of a unidirectional and differentially driven transmitter signal pair and a unidirectional and differentially driven receiver signal pair, wherein K and N are independently whole positive integers equal to or greater than 1.

US Patent:

8010860, Aug 30, 2011

Filed:

Oct 22, 2007

Appl. No.:

11/875972

Inventors:

Peter Joel Jenkins - Colchester VT, US
Paul Joseph Mattos - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04L 1/14

US Classification:

714748, 714807, 370394, 710310

Abstract:

A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

US Patent:

20050256984, Nov 17, 2005

Filed:

May 13, 2004

Appl. No.:

10/844530

Inventors:

Peter Jenkins - Colchester VT, US
Paul Mattos - Jericho VT, US
Stanley Stanski - Essex Junction VT, US

International Classification:

G06F013/00

US Classification:

710100000

Abstract:

The invention is directed to determining the link integrity using information in a industry standard connection protocol, such as the Peripheral Component Interconnect Express industry standard system level bus interconnect protocol. One or more features required in the industry standard protocol are used to implement a loopback master and a loopback slave in an interface device (also referred to as an interface) and an external component or device. Using such features may consume less logic area and provide a robust environment for checking link integrity and capabilities.

US Patent:

20070019570, Jan 25, 2007

Filed:

Aug 25, 2006

Appl. No.:

11/510207

Inventors:

Peter Jenkins - Colchester VT, US
Francis Kampf - Jeffersonville VT, US

International Classification:

H04L 12/28

US Classification:

370258000

Abstract:

A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

US Patent:

57086133, Jan 13, 1998

Filed:

Jul 22, 1996

Appl. No.:

8/681152

Inventors:

Francis Anthony Creed - Jericho VT
Mark Beiley - Chandler AZ
Charles Edward Drake - Underhill VT
Peter Joel Jenkins - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 700

US Classification:

365200

Abstract:

The preferred embodiment of the present invention provides a memory system for use in a computer system that improves the performance of a bit redundancy steering mechanism. The preferred embodiment provides a timing signal path to the bit steering mechanism with a delay shorter than that to the memory data array. Additionally, the required address signals are provided to the bit steering mechanism before the addresses are provided to the memory data array. This is preferably accomplished by bypassing the buffers and providing the address signals directly to the bit steering mechanism.