Peter J Kuhn

US Patent:

7259999, Aug 21, 2007

Filed:

Oct 26, 2005

Appl. No.:

11/258745

Inventors:

Ronald J. Syzdek - Austin TX, US
Gowrishankar L. Chindalore - Austin TX, US
Paul A. Ingersoll - Austin TX, US
Peter J. Kuhn - Austin TX, US

Assignee:

Freescale Semiconductor, Inc - Austin TX

International Classification:

G11C 7/10

US Classification:

36518904, 36518529, 36518514

Abstract:

A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.

US Patent:

7745161, Jun 29, 2010

Filed:

Dec 19, 2003

Appl. No.:

10/740776

Inventors:

Francisco E. Torres - San Jose CA, US
Richard H. Bruce - Los Altos CA, US
James R. Williamson - Del Mar CA, US
Peter Kuhn - Del Mar CA, US
Ray Stevens - La Jolla CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA
The Scripps Research Institute - La Jolla CA

International Classification:

G01N 33/53

US Classification:

435 791, 435 4, 435194, 435183, 435 18

Abstract:

Provided is a method of detecting characteristics of a reaction of interest, including instituting the reaction of interest, obtaining an amplified heat related to the reaction of interest, measuring the amplified heat, and determining the characteristics of the reaction of interest, using the signal obtained in the step of measuring.

US Patent:

7782664, Aug 24, 2010

Filed:

May 30, 2008

Appl. No.:

12/130186

Inventors:

Horacio P. Gasquet - Austin TX, US
Richard K. Eguchi - Austin TX, US
Peter J. Kuhn - Austin TX, US
Ronald J. Syzdek - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/34

US Classification:

36518502, 36518524

Abstract:

An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.

US Patent:

7955877, Jun 7, 2011

Filed:

Mar 17, 2009

Appl. No.:

12/405308

Inventors:

Mohammed Suhail - Austin TX, US
Ko-Min Chang - Austin TX, US
Peter J. Kuhn - Austin TX, US
Erwin J. Prinz - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/26
H01L 21/66

US Classification:

438 17, 438 14, 438 15

Abstract:

Testing a non volatile memory by exposing the non volatile memory to particle radiation (e. g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

US Patent:

8289773, Oct 16, 2012

Filed:

Nov 9, 2010

Appl. No.:

12/942260

Inventors:

Richard K. Eguchi - Austin TX, US
Jon S. Choy - Austin TX, US
Richard K. Glaeser - Lakeway TX, US
Chen He - Austin TX, US
Peter J. Kuhn - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 11/34

US Classification:

36518517, 36518518, 36518519, 36518522, 36518524, 36518529, 36518533

Abstract:

A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.

US Patent:

8504884, Aug 6, 2013

Filed:

Oct 29, 2009

Appl. No.:

12/608405

Inventors:

Richard K. Eguchi - Austin TX, US
Thomas S. Harp - Austin TX, US
Thomas Jew - Austin TX, US
Peter J. Kuhn - Austin TX, US
Timothy J. Strauss - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G11C 29/00

US Classification:

714721, 714723, 714773

Abstract:

A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

US Patent:

20070065934, Mar 22, 2007

Filed:

Nov 27, 2006

Appl. No.:

11/604439

Inventors:

Francisco Torres - San Jose CA, US
Richard Bruce - Los Altos CA, US
James Williamson - Del Mar CA, US
Peter Kuhn - Del Mar CA, US
Ray Stevens - La Jolla CA, US

International Classification:

C12M 3/00
C12Q 1/48
C12Q 1/34
C12Q 1/26

US Classification:

435287100, 435018000, 435025000, 435015000

Abstract:

Provided is a method of detecting characteristics of a reaction of interest, including instituting the reaction of interest, obtaining an amplified heat related to the reaction of interest, measuring the amplified heat, and determining the characteristics of the reaction of interest, using the signal obtained in the step of measuring.

US Patent:

20130322152, Dec 5, 2013

Filed:

May 31, 2012

Appl. No.:

13/484326

Inventors:

Peter J. Kuhn - Austin TX, US
Feng Zhou - Austin TX, US

Assignee:

FREESCALE SEMICONDUCTOR, INC. - Austin TX

International Classification:

G11C 11/00
H01L 21/66

US Classification:

365148, 438 17, 257E21004, 257E21521

Abstract:

A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.