Peter D Morrison

US Patent:

51557355, Oct 13, 1992

Filed:

Mar 31, 1988

Appl. No.:

7/176801

Inventors:

Robert C. Nash - Chelmsford MA
Peter A. Morrison - Framingham MA

Assignee:

Wang Laboratories, Inc. - Lowell MA

International Classification:

G06F 1110
G06F 1340
G06F 1342

US Classification:

371 491

Abstract:

Apparatus and methods for performing parity checking in an environment in which devices which perform parity checking and those which do not are connected to the same synchronous bus. The bus includes a parity enable line, which carries a parity enable signal indicating that the device transmitting data on the bus is a parity device which provides the parity of the data it transmits, a parity line, which carries the parity of the data being transmitted, and a parity error line which carries a parity error signal indicating whether the receiving device detected a parity error. The data is transmitted in a first bus cycle, the parity enable signal and the parity are transmitted in the following bus cycle, and the receiving device transmits the parity error signal in the next bus cycle after that. The bus interface for each parity device includes a parity generator and logic which generates the parity and parity enable signals and receives the parity error signal when the parity device is transmitting and which receives the parity and parity enable signals and generates the parity error signal when the device is receiving. The apparatus is used with system diagnostic apparatus which records the occurrence of any parity error among devices attached to the bus.

US Patent:

45396825, Sep 3, 1985

Filed:

Apr 11, 1983

Appl. No.:

6/484107

Inventors:

Jan S. Herman - Holliston MA
Peter A. Morrison - Framingham MA
Gerald P. Richards - Framingham MA

Assignee:

The United States of America as represented by the Secretary of the Army - Washington DC

International Classification:

G06F 1100

US Classification:

371 15

Abstract:

Method and apparatus permitting a multi-module digital system, such as a puter, having built-in test hardware associated with each module, including a plurality of signal processing units to communicate over two wire circuitry not only the existence of a failure of a particular module, but also its causality. This is accomplished by means of a four state signaling circuit interposed between each signal processing unit of a particular module and a module built-in test circuit which operates once an error output is reported by a signal processing unit to provide a further four state indication of the details of the failure.