Peter R Vigil

US Patent:

59517026, Sep 14, 1999

Filed:

Apr 4, 1997

Appl. No.:

8/832922

Inventors:

Hank Lim - Mountain View CA
Earl T. Cohen - Fremont CA
Peter J. Vigil - San Jose CA
Jengwei Pan - San Jose CA
James S. Blomgren - San Jose CA

Assignee:

S3 Incorporated - Santa Clara CA

International Classification:

G11C 2900
C11C 700

US Classification:

714718

Abstract:

A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths. Non-storage macrocells such as logic gates and buffers can be read but not written using the pass transistors connected to true and complement nodes in the macrocell.