Peter D Wagner

US Patent:

48376248, Jun 6, 1989

Filed:

Apr 30, 1987

Appl. No.:

7/045693

Inventors:

Jurgen Heitmann - Alsbach-Hahnlein, DE
Peter Wagner - Bedford Hills NY

Assignee:

Robert Bosch GmbH - Stuttgart

International Classification:

H04N 514

US Classification:

358166

Abstract:

Digital video signals are subjected to band limiting by a high pass filter with a pass band terminating somewhat above half of the digital sampling frequency. The filtered signal is in effect subtracted from the original signal in an addition circuit with suitably phased inputs in order to make available a substitute signal of the interpolation low pass filtered kind. A circuit for determining the presence of an erroneous digital word accepts the high pass filtered signal, differentiates it twice and then digitally rectifies it in order to detect a possible maximum at half the sampling rate. When such a maximum is found, a changeover switch is caused to substitute the interpolation-low-pass-filtered signal for the orginal signal. Only a single digital filter is necessary for this operation. The high pass filter is a FIR filter of, for example, eleventh order and the middle coefficient is in effect changed from minus 1 to 0 when the delay equalized original signal is added to the output of the high pass filter.

US Patent:

48254401, Apr 25, 1989

Filed:

Apr 30, 1987

Appl. No.:

7/045692

Inventors:

Jurgen Heitmann - Alsbach-Hahnlein, DE
Peter Wagner - New York NY

Assignee:

Robert Bosch GmbH - Stuttgart

International Classification:

G06F 1112

US Classification:

371 31

Abstract:

Two logic circuits (4A, 4B) are utilized in alternation for controlling the processing of successive pixels that are detected to be erroneous. Each logic circuit has its own counter 5A and 5B for associating the undisturbed pixels with ordinal numbers designating their spacing from the disturbed pixel under processing and likewise has a separate PROM (6A, 6B) and a separate multiplier for weighting the undisturbed pixel values, as well as an accumulator (10A, 10B) for summing the weighted values to produce a substitute value, so that undisturbed pixels lying between two disturbed pixels can all be used, where necessary, both for compensating for a preceding disturbed pixel and a following disturbed pixel. When a following disturbed pixel is detected while a preceding disturbed pixel is being processed by a logic circuit, that logic circuit provides a special reset to its counter and accumulator and selects another PROM program in accordance with the shortening of the "filter length" by the nearness of the two disturbed pixels. When no defective pixels appear on the counters, multipliers and accumulators do not need to operate.