Peter D Walters

US Patent:

60612517, May 9, 2000

Filed:

Sep 8, 1997

Appl. No.:

8/925423

Inventors:

Brian R. Hutchison - Windsor CA
Peter Walters - Santa Rosa CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H05K 702

US Classification:

361820

Abstract:

A vertical interconnect package for electronic components and a method to manufacture same. The invention provides a tripartite lead frame-based Vertical Interconnect Package (VIP) which provides integrated feedthrough and integrated shielding in a non-ceramic package. One frame functions as the substrate for coupling the IC device, the second lead frame and third lead frames form shielding and feedthroughs, with the third also providing a lid whereby an airtight chamber around the IC is formed. The invention provides a ground button (the shortest path to the die) divided into n sections providing additional RF and separate ground paths; lead frame connections are used for DC. A method for assembling includes batch lead frame assembly and test prior to singulation. The VIP provides improved performance at lower manufacturing cost and provides easy interfaces to the printed circuit board in surface mount technology manufacturing and is compatible with die mount technologies such as flip-chip.