Peter Wohl

US Patent:

6385750, May 7, 2002

Filed:

Sep 1, 1999

Appl. No.:

09/387865

Inventors:

Rohit Kapur - Cupertino CA
Thomas W. Williams - Boulder CO
John Waicukauski - Tualatin OR
Peter Wohl - Williston VT

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1100

US Classification:

714738, 714724

Abstract:

A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e. g.

US Patent:

6807646, Oct 19, 2004

Filed:

Mar 4, 2002

Appl. No.:

10/091614

Inventors:

Thomas W. Williams - Boulder CO
Peter Wohl - Williston VT
John A. Waicukauski - Tualatin OR
Rohit Kapur - Cupertino CA

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 1100

US Classification:

714736, 714724, 714228

Abstract:

A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of âcareâ bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.

US Patent:

6950974, Sep 27, 2005

Filed:

Sep 7, 2001

Appl. No.:

09/950292

Inventors:

Peter Wohl - Williston VT, US
John A. Waicukauski - Tualatin OR, US
Thomas W. Williams - Boulder CO, US

Assignee:

Synopsys Inc. - Mountain View CA

International Classification:

G01R031/28

US Classification:

714733, 714728

Abstract:

Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.

US Patent:

6959272, Oct 25, 2005

Filed:

Jul 23, 1999

Appl. No.:

09/360069

Inventors:

Peter Wohl - Williston VT, US
John Waicukauski - Tualatin OR, US
Timothy G. Hunkler - Mesa AZ, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F013/10

US Classification:

703 20, 711104, 717109

Abstract:

A method and system for constructing a structural model of a memory for use in ATPG (Automatic Test Pattern Generation). According to an embodiment of the present invention, behavioral models of memories of the simulation libraries are re-coded into simplified behavioral models using behavioral hardware description language (e. g. , Verilog). Then, the simplified behavioral models are automatically converted into structural models that include ATPG memory primitives. The structural models are then stored for subsequent access during pattern generation. In one embodiment, for modeling random access memories (RAMs), the ATPG memory primitives include memory primitives, data bus primitives, address bus primitives, read-port primitives and macro output primitives. In another embodiment, for modeling content addressable memories (CAMs), the ATPG memory primitives include memory primitives, compare port primitives and macro output primitives. An advantage of the present invention is that functional equivalence between the simplified behavioral models and the simulation models can be easily verified with the same behavioral hardware description language simulator (e. g.

US Patent:

6993694, Jan 31, 2006

Filed:

Apr 5, 2002

Appl. No.:

10/117747

Inventors:

Rohit Kapur - Cupertino CA, US
Thomas W. Williams - Boulder CO, US
Tony Taylor - Mountain View CA, US
Peter Wohl - Williston VT, US
John A. Waicukauski - Tualatin OR, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G01R 31/28
G01R 31/08

US Classification:

714733, 324527

Abstract:

A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.

US Patent:

7237162, Jun 26, 2007

Filed:

Oct 1, 2002

Appl. No.:

10/263334

Inventors:

Peter Wohl - Williston VT, US
John A. Waicukauski - Tualatin OR, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G01R 31/28

US Classification:

714726, 714738, 714729

Abstract:

A BIST architecture that allows efficient compression and application of deterministic ATPG patterns while tolerating uncertain bits is provided. In accordance with one feature of the invention, a large number of short scan chains can be configured between a decompressor and an observe selector. The observe selector selectively presents values of specific scan chains or scan cells to an external tester, thereby significantly reducing test data and test cycles. Advantageously, the core of the tested device is not changed as would be the case in BIST architectures including MISRs. Moreover, test points or logic to block uncertain bits do not need to be inserted. Furthermore, the loaded care bits for the scan chains as well as the bits for controlling the observe selector can be deterministically controlled, thereby providing optimal testing flexibility.

US Patent:

7814444, Oct 12, 2010

Filed:

May 25, 2007

Appl. No.:

11/807119

Inventors:

Peter Wohl - Williston VT, US
John A. Waicukauski - Tualatin OR, US
Sanjay Ramnath - San Jose CA, US
Rohit Kapur - Cupertino CA, US
Thomas W. Williams - Boulder CO, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 1, 716 5

Abstract:

A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

US Patent:

7823034, Oct 26, 2010

Filed:

Apr 13, 2007

Appl. No.:

11/786968

Inventors:

Peter Wohl - Williston VT, US
John A Waicukauski - Tualatin OR, US
Frederic J Neuveux - Meylan, FR

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G01R 31/28
G06F 17/50

US Classification:

714726, 714729, 714733, 714741, 714742, 716 4

Abstract:

An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.