Peter C Yu

US Patent:

6484065, Nov 19, 2002

Filed:

Oct 5, 1998

Appl. No.:

09/166498

Inventors:

Peter K. Yu - Sunnyvale CA
Michael D. Rostoker - Boulder Creek CA

Assignee:

Kawasaki Microelectronics, Inc. - Chiba

International Classification:

G06F 1900

US Classification:

700121, 700 2, 700 4, 700 5, 700117, 711105, 711112, 716 2, 716 3, 716 4, 365149, 36523003, 712 1, 712 10, 712 16

Abstract:

An efficient DSP or MPU is combined with efficient DRAM on a single IC die. To optimize the embedded memory, the chip includes wide-band connections to DRAM. Row and column addresses of DRAM can be applied at the same time using wide address busses. Additional metal lines lower the resistance of the word line in the DRAM circuits. For certain process steps, the processor block is masked off and the process steps unique to the fabrication of memory are performed on the memory block, and vice-versa. Process steps which are common to the processor and memory blocks can be performed simultaneously on the processor and memory blocks without masking off either block. Certain process steps can be employed in the fabrication of the one of the two processor and memory blocks in addition to or in lieu of processes normally used in the fabrication of that block. An electronic component (e. g. , integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

US Patent:

20200287001, Sep 10, 2020

Filed:

May 25, 2020

Appl. No.:

16/882542

Inventors:

Guobiao ZHANG - Corvallis OR, US
Peter Y. YU - Oakland CA, US

Assignee:

HangZhou HaiCun Information Technology Co., Ltd. - HangZhou

International Classification:

H01L 29/20
H01L 23/00
H01L 27/088
H01L 27/06
H01L 21/8252
H01L 21/66

Abstract:

A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. Multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. The normal transistors are connected in serial, while the defective transistors are not connected.

US Patent:

20190198624, Jun 27, 2019

Filed:

Dec 24, 2018

Appl. No.:

16/231934

Inventors:

Guobiao ZHANG - Corvallis OR, US
Peter Y. YU - Oakland CA, US

Assignee:

HangZhou HaiCun Information Technology Co., Ltd. - HangZhou

International Classification:

H01L 29/20
H01L 27/088
H01L 23/00

Abstract:

A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.