Philip Michael Rogers

US Patent:

20180321946, Nov 8, 2018

Filed:

Jul 19, 2018

Appl. No.:

16/040224

Inventors:

- Santa Clara CA, US
Mark Leather - Los Gatos CA, US
Michael Mantor - Orlando FL, US
Rex McCrary - Orlando FL, US
Sebastien Nussbaum - Boxborough MA, US
Philip J. Rogers - Austin TX, US
Ralph Clay Taylor - Deland FL, US
Thomas Woller - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G06F 9/38
G06T 1/20
G06F 9/48

Abstract:

A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

US Patent:

20180239722, Aug 23, 2018

Filed:

Apr 20, 2018

Appl. No.:

15/958805

Inventors:

- Santa Clara CA, US
Philip J. Rogers - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G06F 13/16

Abstract:

A method, computer program product, and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method can include associating a first memory buffer to a first plurality of memory banks, where the first plurality of memory banks spans over a first set of one or more memory channels. Similarly, the method can include associating a second memory buffer to a second plurality of memory banks, where the second plurality of memory banks spans over a second set of one or more memory channels. The method can also include associating a first sequence identifier and a second sequence identifier with the first memory buffer and the second memory buffer, respectively. Further, the method can include accessing the first and second memory buffers based on the first and second sequence identifiers.

US Patent:

20170076421, Mar 16, 2017

Filed:

Nov 28, 2016

Appl. No.:

15/362230

Inventors:

- Sunnyvale CA, US
Ralph Clayton Taylor - Deland FL, US
Michael Mantor - Orlando FL, US
Kevin John McGrath - Los Gatos CA, US
Sebastien Nussbaum - Boxborough MA, US
Nuwan Jayasena - Sunnyvale CA, US
Rex McCrary - Orlando FL, US
Mark Leather - Los Gatos CA, US
Philip J. Rogers - Austin TX, US
Thomas Woller - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06T 1/20
G06F 9/52
G06T 1/60

Abstract:

Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

US Patent:

20160378674, Dec 29, 2016

Filed:

Jun 23, 2015

Appl. No.:

14/747944

Inventors:

- Markham, CA
- Sunnyvale CA, US
Philip J. Rogers - Austin TX, US
Benjamin T. Sander - Austin TX, US
Anthony Asaro - Toronto, CA
Mike Mantor - Orlando FL, US
Raja Koduri - Sunnyvale CA, US

International Classification:

G06F 12/10

Abstract:

A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.