Phillip Edward Byrd

US Patent:

6374376, Apr 16, 2002

Filed:

Sep 3, 1998

Appl. No.:

09/146629

Inventors:

Phillip E. Byrd - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

714718, 714738

Abstract:

An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.

US Patent:

6410352, Jun 25, 2002

Filed:

May 14, 2001

Appl. No.:

09/854541

Inventors:

Tim Damon - Meridian ID
Phillip E. Byrd - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2166

US Classification:

438 14, 438 15, 438 16, 324537, 324550, 324525, 324527

Abstract:

A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested.

US Patent:

6424161, Jul 23, 2002

Filed:

Sep 3, 1998

Appl. No.:

09/146688

Inventors:

Tim Damon - Meridian ID
Phillip E. Byrd - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3102

US Classification:

324550, 324537, 324677

Abstract:

A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested.

US Patent:

6760871, Jul 6, 2004

Filed:

Aug 3, 2001

Appl. No.:

09/921767

Inventors:

Phillip E. Byrd - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 2900

US Classification:

714718, 714738, 365201

Abstract:

An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.

US Patent:

6762608, Jul 13, 2004

Filed:

Jun 25, 2002

Appl. No.:

10/179543

Inventors:

Tim Damon - Meridian ID
Phillip E. Byrd - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01H 8530

US Classification:

324550, 324537, 324763, 365201, 714736

Abstract:

A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested.

US Patent:

6809378, Oct 26, 2004

Filed:

Aug 30, 2001

Appl. No.:

09/941761

Inventors:

Phillip E. Byrd - Boise ID
Paul R. Sharratt - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H07L 31392

US Classification:

257347

Abstract:

The invention provides an apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.

US Patent:

6819132, Nov 16, 2004

Filed:

Dec 20, 2002

Appl. No.:

10/327468

Inventors:

Phillip E. Byrd - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3126

US Classification:

324765

Abstract:

Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e. g. , probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.

US Patent:

6819161, Nov 16, 2004

Filed:

Oct 11, 2002

Appl. No.:

10/268901

Inventors:

Phillip E. Byrd - Boise ID
Paul R. Sharratt - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01F 110

US Classification:

327536

Abstract:

The invention provides an apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.