Phillip D Johnson

US Patent:

55766641, Nov 19, 1996

Filed:

Nov 2, 1995

Appl. No.:

8/556882

Inventors:

Barry W. Herold - Boca Raton FL
Scott R. Humphreys - Boynton Beach FL
Phillip Johnson - Lake Worth FL
Raymond L. Barrett - Ft. Lauderdale FL
Grazyna A. Pajunen - Delray Beach FL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 7093

US Classification:

331 1A

Abstract:

A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).