Phillip W Matthews

US Patent:

6373954, Apr 16, 2002

Filed:

Oct 14, 1997

Appl. No.:

08/949563

Inventors:

Jeff Klaas - Austin TX
Mark Gentry - Austin TX
Phillip Matthews - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

H04B 100

US Classification:

381119, 700 94

Abstract:

A single chip audio system includes a bus interface , digital to analog converters , an analog mixer , and analog spatial enhancement circuitry. Digital to analog converters convert digital audio data received through bus interface into analog signals. Analog mixer mixes signals received from digital to analog converters with an analog signal received from an external source. Analog spatial enhancement circuitry enhances first and second mixed analog signals output from analog mixer.

US Patent:

6405093, Jun 11, 2002

Filed:

Feb 26, 1998

Appl. No.:

09/031439

Inventors:

Jeff Klaas - Austin TX
Mark Gentry - Austin TX
Phillip Matthews - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 1700

US Classification:

700 94, 381 64, 381107

Abstract:

Amplitude control circuitry includes a first register for storing received amplitude control data and a second register for storing amplitude control data transfered from first register. Output circuitry controls the amplitude of a received signal in response to amplitude data transferred from second register. A sensor determines when data stored in first register and second register does not match and enables a comparator when data in first register and, second register does not match. Comparator compares a signal output from output circuitry with a reference signal and generates a signal for enabling the transfer of data from first register to second register when the signal output from output circuitry falls within a window defined by the reference voltage.

US Patent:

6628999, Sep 30, 2003

Filed:

Feb 26, 1998

Appl. No.:

09/031112

Inventors:

Jeff Klaas - Austin TX
Phillip Matthews - Austin TX

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

G06F 1700

US Classification:

700 94, 381104, 381107

Abstract:

An audio system includes circuitry for generating an audio data stream and circuitry for generating digital words defining a volume control level. System also includes volume control circuitry for controlling the amplitude of the audio data stream in response to the digital words. Volume control circuitry includes a master register for holding digital words received from circuitry for generating and a slave register for holding a digital word selectively transferred from master register in response to an enable signal. Output control circuitry and receive the audio data stream and apply a preselected gain defined by the digital word held in slave register. Volume control circuitry also includes circuitry for generating the enable signal when a digital word held in the master register changes and the audio data stream output from ouput control circuitry reaches a zero crossing.

US Patent:

6952621, Oct 4, 2005

Filed:

Nov 20, 2000

Appl. No.:

09/717407

Inventors:

Jeff Klaas - Austin TX, US
Mark Gentry - Austin TX, US
Phillip Matthews - Austin TX, US

Assignee:

Crystal Semiconductor Corp. - Austin TX

International Classification:

G06F017/00
H04B001/00

US Classification:

700 94, 381 1, 381119

Abstract:

A single chip audio system includes a bus interface digital to analog converters an analog mixer and analog spatial enhancement circuitry Digital to analog converters convert digital audio data received through bus interface into analog signals. Analog mixer mixes signals received from digital to analog converters with an analog signal received from an external source. Analog spatial enhancement circuitry enhances first and second mixed analog signals output from analog mixer.

US Patent:

7248848, Jul 24, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/881167

Inventors:

Phillip M. Matthews - Austin TX, US
Frederick A. Rush - Austin TX, US
G. Diwakar Vishakhadatta - Austin TX, US

International Classification:

H04B 1/10

US Classification:

455296, 455310, 455 631, 327295, 327296

Abstract:

A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a first timing circuit that provides timed signals to control timing of system operations during an active mode of operation of the digital processing circuit, and a second timing circuit that provides timing signals to control timing of system operations during an active mode of operation of the radio frequency circuit. In one particular embodiment, at least a portion of the first timing circuit is disabled when the radio frequency circuit is active (receiving and/or transmitting).

US Patent:

7380033, May 27, 2008

Filed:

Jun 30, 2006

Appl. No.:

11/479733

Inventors:

Phillip M. Matthews - Austin TX, US
Frederick A. Rush - Austin TX, US
G. Diwakar Vishakhadatta - Austin TX, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

G06F 13/00
G06F 3/00
H04Q 7/20
H04B 7/00
H04L 25/08
H04N 7/14

US Classification:

710110, 710 37, 455455, 455515, 455528, 348 141, 375346

Abstract:

A communication apparatus includes a radio frequency circuit that operates on a radio frequency signal and a digital processing circuit coupled to the radio frequency circuit. The digital processing circuit includes a plurality of bus masters coupled to a shared bus. A bus arbiter is provided for arbitrating between requests to access the bus by a first bus master and one or more other bus masters. Accesses by the one or more other bus masters to the bus are restricted in response to a signal indicative of a change in a mode of operation of the RF circuit. In one particular implementation, a communication apparatus employs time domain isolation wherein the digital processing circuit may be placed in a shutdown mode when the radio frequency circuit is active.

US Patent:

7433393, Oct 7, 2008

Filed:

Sep 30, 2004

Appl. No.:

10/955926

Inventors:

Shaojie Chen - Austin TX, US
Frederick A. Rush - Austin TX, US
G. Diwakar Vishakhadatta - Austin TX, US
Phillip M. Matthews - Austin TX, US

Assignee:

NXP B.V. - Eindhoven

International Classification:

H04B 1/38

US Classification:

375219, 375222

Abstract:

A method of operating a radio-frequency (RF) circuitry and a signal-processing circuitry in a mobile telephone apparatus includes at least partially disabling the signal-processing circuitry while transmitting or receiving signals. In one example, a processor is efficiently disabled by generating and servicing an interrupt of relatively high priority. One advantage of this example is that preexisting, legacy code can be maintained, while still achieving the desired objectives. The processor can be enabled by generating and servicing a second high priority interrupt.

US Patent:

7593482, Sep 22, 2009

Filed:

Sep 30, 2004

Appl. No.:

10/955569

Inventors:

Xue-Mei Gong - Austin TX, US
Jing Liang - Superior CO, US
Frederick A. Rush - Austin TX, US
Phillip M. Matthews - Austin TX, US
Gannavaram Diwakar Vishakhadatta - Austin TX, US

Assignee:

St-Ericsson SA - Geneva

International Classification:

H03K 9/00

US Classification:

375316, 375357, 375358

Abstract:

A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.