Phuc Vinh Tran

US Patent:

6651208, Nov 18, 2003

Filed:

Apr 4, 2000

Appl. No.:

09/542893

Inventors:

Phuc Thanh Tran - Milpitas CA
Tom Vu - San Jose CA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

H03M 1329

US Classification:

714755, 714763, 714785

Abstract:

The present invention provides a method and system for syndrome generation for data from an optical media. The method includes reading data bytes for a plurality of columns of a row of the data; reading a plurality of partial syndromes from a memory, each of the plurality of partial syndromes corresponding to one of the plurality of columns; updating each of the plurality of partial syndromes with the data byte of the corresponding column; and writing the plurality of updated partial syndromes into the memory. The present invention obtains data bytes for multiple columns at one time. Syndrome generation is then performed for each column, with the partial syndromes for each column stored in a memory. As the data bytes of subsequent rows of data for multiple columns are obtained, the partial syndromes for each column are read from the memory and loaded into a syndrome generation logic, thus updating the partial syndrome for each column. The updated syndromes are written back into the memory.

US Patent:

8332931, Dec 11, 2012

Filed:

Sep 1, 2009

Appl. No.:

12/551758

Inventors:

Phuc Thanh Tran - Fremont CA, US
Bing Xiao - San Jose CA, US
Tze Lei Poo - Sunnyvale CA, US
Peter Nhat Dinh - San Jose CA, US

Assignee:

Marvell International Ltd.

International Classification:

G06F 7/04
G06F 12/14

US Classification:

726 17

Abstract:

Devices, systems, methods, and other embodiments associated with processing commands according to authorization are described. In one embodiment, a chip includes a secure module configured to store secure firmware, and to execute the secure firmware. The secure firmware prevents the secure module from at least partially processing a command that originated from an untrusted source. The chip also includes an unsecure module configured to store unsecure firmware, and to execute the unsecure firmware. The unsecure firmware permits the unsecure module to process a command having originated from an untrusted source. The chip is configured where the unsecure firmware is separately updateable from the secure firmware.

US Patent:

8423789, Apr 16, 2013

Filed:

May 22, 2008

Appl. No.:

12/125670

Inventors:

Tze Lei Poo - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Phuc Thanh Tran - Fremont CA, US
Saeed Azimi - Los Gatos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 21/00

US Classification:

713189, 713193, 380 44

Abstract:

In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key.

US Patent:

62498967, Jun 19, 2001

Filed:

Feb 17, 1999

Appl. No.:

9/251724

Inventors:

Son Hong Ho - Los Altos CA
Hung Cao Nguyen - San Jose CA
Phuc Thanh Tran - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11B 2700
G06F 1100

US Classification:

714814

Abstract:

Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched. Once initial sync is made, the bit timing is adjusted when too many pseudo-sync clocks are inserted for sync marks missed due to jitter.

US Patent:

55026966, Mar 26, 1996

Filed:

Sep 23, 1994

Appl. No.:

8/311069

Inventors:

Tony J. Yoon - San Jose CA
Michael J. McGrath - Sunnyvale CA
Phuc Tran - Milpitas CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 1722

US Classification:

369 32

Abstract:

A subcode R-W channel data de-interleaving and de-scrambling method and apparatus includes the ability to de-interleave and de-scramble the encoded subchannel data without the necessity of storage elements, by dynamically calculating the final location of each byte of data within a packet as it is read from the CD-Rom. A pack counter monitors the pack number of the current byte of data. An index counter monitors the location of the current data within a pack. A subtractor uses the values from the pack counter and the index counter to obtain an input value, a first portion of which is supplied to a first offset generator. A second portion of the subtractor output is used to select a base address. The first offset generator determines the pack number of the current byte of data after the de-interleave process. A second offset generator receives a value from the index counter and generates a corresponding value.

US Patent:

55863060, Dec 17, 1996

Filed:

May 23, 1995

Appl. No.:

8/448098

Inventors:

Paul M. Romano - Boulder CO
Larry D. King - Boulder CO
John S. Geldman - Los Gatos CA
Bhupendra K. Ahuja - Fremont CA
Palaksha Setty - Austin TX
Petro Estakhri - Pleasanton CA
Son Ho - Sunnyvale CA
Phuc Tran - Fremont CA
Maryam Imam - Fremont CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G06F 300

US Classification:

395500

Abstract:

An integrated circuit controls the low level, electromechanical functionality of a computer mass storage device, such as a magnetic disk drive incorporating a spindle motor for rotatably controlling a disk and an actuator for positioning at least one read/write head with respect to the disk, to read or write encoded data configured in information data sectors and to sense encoded data of servo data sectors. A servo subsystem is coupled to an output of the read/write head for detecting the servo data sectors and providing a control signal in response thereto. An analog-to-digital subsystem is also coupled to an output of the read/write head and is operative in response to the servo subsystem control signal for converting the encoded data of the servo data sectors to digital transducer position information representative of a position of the read/write head with respect to the data tracks. A data processing subsystem is coupled to the analog-to-digital subsystem for processing the digital transducer position information and providing digital motion control signals in response thereto. A digital-to-analog subsystem is coupled to the data processing subsystem for providing analog control signals to the spindle motor and the actuator in response to the digital motion control signals.

US Patent:

6195778, Feb 27, 2001

Filed:

Jul 30, 1998

Appl. No.:

9/126125

Inventors:

Phuc Thanh Tran - Milpitas CA

Assignee:

LSI Logic Corp. - Milpitas CA

International Classification:

H03M 1300

US Classification:

714752

Abstract:

A demodulator for digital-versatile disk (DVD) optical disks converts 16-bit codewords stored on the disk into 8-bit symbols or user bytes that are sent to the host after error correction. Rather than use the modulation tables in the DVD specification in reverse, the entries in the modulation table are sorted and combined. The four states stored in the DVD modulation table are reduced to two states or conditions. All entries from states 1 and 4 are sorted into unique tables that have unique mappings of codewords to symbols. Since the unique mappings are not sequence or state dependent, no state information is stored in the unique tables. Entries from states 2 and 3 are sorted into duplicates tables that have duplicate mappings, where a codeword can map to two different symbols, depending on the state sequence. One of the two symbols is chosen based on bits in the following codeword, which is the next state. The next state is stored with each entry in the duplicates tables, while all current state information is deleted from all tables.

US Patent:

55769101, Nov 19, 1996

Filed:

May 15, 1995

Appl. No.:

8/441676

Inventors:

Paul M. Romano - Boulder CO
Larry D. King - Boulder CO
Mike Machado - Boulder CO
Petro Estakhri - Pleasanton CA
Son Ho - Sunnyvale CA
Phuc Tran - Fremont CA
Maryam Imam - Fremont CA

Assignee:

Cirrus Logic, Inc. - Fremont CA

International Classification:

G11B 5596

US Classification:

360 7708

Abstract:

A burst magnitude comparator and an instruction sequencer are employed in a servo system controller to rapidly determine position correction information for moving a transducer head over the center line of a track recorded on a disk in a mass storage disk drive. The burst magnitude comparator selects at least two burst signals derived from bursts recorded at predetermined locations relative to the center line from which to derive a correction control signal, based on a predetermined relationship of the burst signals, and supplies the selected burst signals in a predetermined order to facilitate calculation of the correction signal by a data processor used with the servo system controller. An instruction sequencer controls a sequence of converting the analog burst signals from the head to digital burst signals without intervention or control from the data processor. By ordering the signals with the burst magnitude comparator and by sequencing the conversion of the signals, the calculation is speeded and the processing and code requirements for the data processor are greatly reduced, thereby reducing transport delay and freeing the resources of the processor for use in other, potentially more important tasks associated with the servo controller.