Ping Hong Chen

US Patent:

6385748, May 7, 2002

Filed:

Mar 30, 1999

Appl. No.:

09/281370

Inventors:

Ping Chen - San Jose CA

Assignee:

NEC Electronics, Inc. - Santa Clara CA

International Classification:

G01R 3128

US Classification:

714724, 365201

Abstract:

A method and circuit for allowing direct access logic testing in integrated circuits. In one embodiment, an interface between integrated circuit core logic and integrated circuit user-defined logic is exposed, and the integrated circuit core logic and the integrated circuit user-defined logic is tested via the exposed interface. In another embodiment, an integrated circuit has logic selection circuitry connected with core logic and user-defined logic. The logic selection circuitry is used to selectively test the core logic and user-defined logic.

US Patent:

7325086, Jan 29, 2008

Filed:

Dec 15, 2005

Appl. No.:

11/300980

Inventors:

Roy (Dehai) Kong - Cupertino CA, US
Wen-Chung Chen - Cupertino CA, US
Ping Chen - San Jose CA, US
Irene (Chih-Yiieh) Cheng - San Jose CA, US
Tatsang Mak - Milpitas CA, US
Xi Liu - Shanghai, CN
Li Zhang - ShangHai, CN
Li Sun - Shanghai, CN
Chenggang Liu - Shanghai, CN

Assignee:

Via Technologies, Inc. - Hsin-Tien, Taipei

International Classification:

G06F 13/40

US Classification:

710307, 345503

Abstract:

Supporting multiple graphics processing units (GPUs) comprises a first path coupled to a north bridge device (or a root complex device) and a first GPU, which may include a portion of the first GPU's total communication lanes. A second communication path may be coupled to the north bridge device and a second GPU and may include a portion of the second GPU's total communication lanes. A third communication path may be coupled between the first and second GPUs directly or through one or more switches that can be configured for single or multiple GPU operations. The third communication path may include some or all of the remaining communication lanes for the first and second GPUs. As a nonlimiting example, the first and second GPUs may each utilize an 8-lane PCI express communication path with the north bridge device and an 8-lane PCI express communication path with each other.

US Patent:

7340557, Mar 4, 2008

Filed:

Dec 15, 2005

Appl. No.:

11/300705

Inventors:

Dehai Kong - Cupertino CA, US
Wen-Chung Chen - Cupertino CA, US
Ping Chen - San Jose CA, US
Irene Chih-Yiieh Cheng - San Jose CA, US
Tatsang Mak - Milpitas CA, US
Xi Liu - Shanghai, CN
Li Zhang - ShangHai, CN
Li Sun - Shanghai, CN
Chenggang Liu - Shanghai, CN

Assignee:

Via Technologies, Inc. - Taipei

International Classification:

G06F 13/00
G06F 13/36

US Classification:

710316, 710306, 710311

Abstract:

A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

US Patent:

7567891, Jul 28, 2009

Filed:

Sep 27, 2001

Appl. No.:

09/969185

Inventors:

Zhihong Liu - Cupertino CA, US
Lifeng Wu - Fremont CA, US
Jeong Y. Choi - Palo Alto CA, US
Ping Chen - San Jose CA, US
Alvin I. Chen - San Jose CA, US
Gang Zhang - Campbell CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 7/60
G06F 17/50
G06F 9/45
G01R 15/00
G01R 27/28
G01R 27/26
H03K 19/20
H03K 19/094

US Classification:

703 13, 703 2, 703 14, 716 4, 716 5, 324678, 326117, 326120, 326124, 702 57, 702117

Abstract:

The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added.

US Patent:

7696993, Apr 13, 2010

Filed:

Feb 8, 2007

Appl. No.:

11/672692

Inventors:

Boris Prokopenko - Milpitas CA, US
Hsilin (Stephen) Huang - Milpitas CA, US
Ping Chen - San Jose CA, US

Assignee:

VIA Technologies, Inc. - Hsin-Tien, Taipei

International Classification:

G06T 17/00

US Classification:

345420, 345423, 345441

Abstract:

An input stream of graphics primitives may be converted into to a predetermined output stream of graphics primitives by a processor in a graphics pipeline. The processor recognizes a predetermined sequence pattern in the input stream of graphics primitives to the processor. The processor determines whether the recognized sequence pattern can be converted into the one of the plurality of predetermined output streams of graphics primitives. If so, the processor identifies a number of vertices in the recognized sequence pattern and reorders the vertices into a predetermined output pattern. Thereafter, the processor outputs the predetermined output pattern corresponding to one or more graphics processing components.

US Patent:

7263477, Aug 28, 2007

Filed:

Jun 9, 2003

Appl. No.:

10/457945

Inventors:

Ping Chen - San Jose CA, US
Zhihong Liu - Cupertino CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 13, 703 14, 703 2, 703 15, 716 1, 716 4, 700 31

Abstract:

The present invention includes a method for modeling devices having different geometries, in which a range of interest for device geometrical variations is divided into a plurality of subregions each corresponding to a subrange of device geometrical variations. The plurality of subregions include a first type of subregions and a second type of subregions. The first or second type of subregions include one or more subregions. A regional global model is generated for each of the first type of subregions and a binning model is generated for each of the second type of subregions. The regional global model for a subregion uses one set of model parameters to comprehend the subrange of device geometrical variations corresponding to the G-type subregion. The binning model for a subregion includes binning parameters to provide continuity of the model parameters when device geometry varies across two different subregions.

US Patent:

20030220779, Nov 27, 2003

Filed:

Mar 31, 2003

Appl. No.:

10/404630

Inventors:

Ping Chen - San Jose CA, US
Jushan Xie - Campbell CA, US

International Classification:

G06F017/50
G06F009/45

US Classification:

703/014000, 703/022000

Abstract:

The present invention includes a method for extracting semiconductor device model parameters for a device model such as the BSIMPD model. The method comprises obtaining terminal current data corresponding to various bias conditions in a set of test devices and extracting a portion of a plurality of DC model parameters for the device model from the terminal current data. The terminal current are then modified based on the extracted portion of the DC model parameters before extracting additional DC model parameters. The present invention also includes novel methods for extracting some of the DC model parameters.

US Patent:

20040073879, Apr 15, 2004

Filed:

May 15, 2003

Appl. No.:

10/439755

Inventors:

Ping Chen - San Jose CA, US
Xisheng Zhang - Sunnyvale CA, US

International Classification:

G06F017/50

US Classification:

716/008000, 716/004000, 703/002000, 703/014000

Abstract:

The present invention includes a method for generating typical and corner device models to account for statistical variations in a semiconductor device fabrication process. The typical and corner models can be generated before the semiconductor device fabrication process is fully developed based on a process specification associated with the semiconductor device fabrication process. The typical and corner models can also be generated with better accuracy after the semiconductor device fabrication process is developed and measured data are available for model generation.