Ping Wu

US Patent:

6366979, Apr 2, 2002

Filed:

Dec 16, 1997

Appl. No.:

08/991845

Inventors:

Pidugu L. Narayana - Santa Clara CA
Daniel Eric Cress - Starkville MS
Ping Wu - Austin TX

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1200

US Classification:

711109, 711118, 711154, 365220, 365221, 365230

Abstract:

A memory circuit that allows for short retransmit recovery times by implementing a read cache memory in a FIFO device. A circuit comprising a memory array, a cache memory and a logic circuit. The memory array includes a read pointer, a write pointer and a plurality of memory rows. The cache memory is configured to store one or more memory data bits. The logic circuit is further configured to control the output of the circuit by presenting either (i) an output from the memory array or (ii) an output from the cache memory.

US Patent:

6424022, Jul 23, 2002

Filed:

Mar 12, 2000

Appl. No.:

09/523558

Inventors:

Ping Wu - Cupertino CA
Chinpo Chen - Milpitas CA

Assignee:

Mobilink Telecom, Inc. - Santa Clara CA

International Classification:

H01L 2358

US Classification:

257665, 257547, 257659

Abstract:

A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise generating circuit blocks and noise sensitive circuit blocks. N-type and P-type diffusion guard rings are placed around each of the circuit blocks. Substantially overlying the N-type and P-type diffusion guard rings are power supply meshes which are intimately in contract with the guard rings below through spaced apart vias. The power supply meshes not only supply power for the circuit blocks, but also reverse-bias the diffusion guard rings for improved noise isolation.

US Patent:

6586292, Jul 1, 2003

Filed:

Jun 22, 2002

Appl. No.:

10/177229

Inventors:

Ping Wu - Cupertino CA
Chinpo Chen - Milpitas CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 218238

US Classification:

438215, 257432, 257 48, 257547, 257659

Abstract:

A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise generating circuit blocks and noise sensitive circuit blocks. N-type and P-type diffusion guard rings are placed around each of the circuit blocks. Substantially overlying the N-type and P-type diffusion guard rings are power supply meshes which are intimately in contract with the guard rings below through spaced apart vias. The power supply meshes not only supply power for the circuit blocks, but also reverse-bias the diffusion guard rings for improved noise isolation.

US Patent:

6770963, Aug 3, 2004

Filed:

Jan 4, 2001

Appl. No.:

09/754900

Inventors:

Ping Wu - Cupertino CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 2352

US Classification:

257691, 257784

Abstract:

A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip power bonding pads connected to corresponding first, second, and third chip power supply nets, the chip power bonding pads disposed adjacent to a chip periphery defining the chip area, the scalable multi-power integrated circuit package comprising: a central chip mounting area for mounting one of said integrated circuits, said chip mounting area defining a chip mounting area periphery surrounding said chip mounting area; spaced apart first, second and third package power supply continuous conductive traces, each trace disposed adjacent to the chip area mounting periphery; corresponding first, second and third pluralities of spaced apart package bonding areas defined along each respective one of said first, second and third package power supply continuous conductive traces, each respective one of said package bonding areas disposed in bondable alignment with a corresponding one of said chip power bonding pads along said chip periphery such that a permanent conductive bond can be made between said package bonding area and said chip bonding pad. Alternatives include a chip scale package outline, in which one of the chip power supply nets is a common ground return for the other two power supply nets.

US Patent:

6897572, May 24, 2005

Filed:

Feb 21, 2003

Appl. No.:

10/371216

Inventors:

Datong Chen - Fremont CA, US
Ping Wu - Cupertino CA, US
Qiu Sha - Sunnyvale CA, US

Assignee:

Spreadtrum Communications Corporation - Sunnyvale CA

International Classification:

H01L023/50
H01L021/00

US Classification:

257798, 438800

Abstract:

An integrated circuit including a power ring and an embedded low drop-off voltage regulator is disclosed herein. The regulator is located within an inner side of the power ring. An input of the regulator is coupled to the power ring. An output of the regulator is coupled to a circuit also included in the integrated circuit. The regulator is configured to fit within a bond pad frame.

US Patent:

7129574, Oct 31, 2006

Filed:

Jul 2, 2004

Appl. No.:

10/884055

Inventors:

Ping Wu - Cupertino CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H01L 23/52

US Classification:

257691, 257784

Abstract:

A scalable multi-power integrated circuit package for integrated circuits having spaced apart first, second and third pluralities of respective spaced apart chip power bonding pads connected to-corresponding first, second, and third chip power supply nets, the chip power bonding pads disposed adjacent to a chip periphery defining the chip area, the scalable multi-power integrated circuit package comprising: a central chip mounting area for mounting one of said integrated circuits, said chip mounting area defining a chip mounting area periphery surrounding said chip mounting area; spaced apart first, second and third package power supply continuous conductive traces, each trace disposed adjacent to the chip area mounting periphery; corresponding first, second and third pluralities of spaced apart package bonding areas defined along each respective one of said first, second and third package power supply continuous conductive traces, each respective one of said package bonding areas disposed in bondable alignment with a corresponding one of said chip power bonding pads along said chip periphery such that a permanent conductive bond can be made between said package bonding area and said chip bonding pad. Alternatives include a chip scale package outline, in which one of the chip power supply nets is a common ground return for the other two power supply nets.

US Patent:

8058063, Nov 15, 2011

Filed:

Jun 19, 2002

Appl. No.:

10/176971

Inventors:

Ping Wu - League City TX, US

Assignee:

Board of Regents, The University of Texas System - Austin TX

International Classification:

C12N 5/02

US Classification:

435377, 435384, 435402, 424 937

Abstract:

A method of priming neural stem cells in vitro by adhesively culturing in a mixture of basic fibroblast growth factor, laminin and heparin to differentiate into specific neuronal phenotypes, including cholinergic, glutamatergic and GABAergic neurons, in a region-specific manner, when transplanted in vivo.

US Patent:

8229464, Jul 24, 2012

Filed:

Dec 30, 2009

Appl. No.:

12/649967

Inventors:

Ping Wu - San Bruno CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

H04W 24/00

US Classification:

4554561, 4554562, 4554563, 4554566, 4554565, 4554141

Abstract:

A system and method identifies correlations between locations. A server may receive information identifying an action and a location from a plurality of users. The server may assign a weighted value to each action and store the weighted value and location in a database. The database may be used to generate vector data for each location identifying the weighted values for a number of users. In response to receiving a location from a particular user device, the server may identify a vector associated with the received location. The location vector may be compared to other location vectors to determine if there is any correlation between the vectors. Where the server identifies a correlated vector, the server may send the identification of the corresponding location or information associated with the corresponding location to the particular user device.