Ping Yang

US Patent:

6535742, Mar 18, 2003

Filed:

Jun 29, 1999

Appl. No.:

09/342397

Inventors:

Hua Jiang - Plano TX
Chang Yu - Plano TX
Ping Yang - Plano TX
Hee Lee - Plano TX

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04Q 720

US Classification:

455452, 455 62, 455 63, 455444

Abstract:

The present invention is directed to a method and apparatus for assigning channels in a cellular environment. A time period T is defined in which cellular operational measurement information such as traffic information and mobility information are collected. Channels that are available for allocation are collected and maintained in a matrix. The predicted number of channels are calculated based on the operational measurement information. Using the channels available for allocation and the predicted number of channels, channels are allocated for use. As the operational measurement information changes the time period T is adjusted to accommodate the changes in traffic or mobility within the cellular system.

US Patent:

6628637, Sep 30, 2003

Filed:

Dec 15, 1999

Appl. No.:

09/464667

Inventors:

Huan Li - Plano TX
Ping Yang - Plano TX

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04Q 720

US Classification:

370342, 370331, 370332, 370335, 455436, 455522

Abstract:

A new call blocking threshold of one or more BTS forward links is adjusted to compensate for variation in traffic demand and, optionally, user mobility as well. Anticipated traffic demand from new calls and user mobility are derived from operational measurement data obtained and stored in a management and control system. The new call blocking threshold is adjusted with a frequency relating to the rate of change in traffic demand or user mobility.

US Patent:

59783583, Nov 2, 1999

Filed:

Apr 4, 1997

Appl. No.:

8/833362

Inventors:

Jing Wang - Plano TX
Eddy H. Trink - Plano TX
Ping Yang - Plano TX
Seshagiri R. Madhavapeddy - Richardson TX

Assignee:

Nortel Networks Corporation - Richardson TX

International Classification:

G01R 3108
G06F 1100
G08C 1500
H04M 1500

US Classification:

370234

Abstract:

The switch capacity prediction process of the present invention collects operational measurements from the cellular switch. These operational measurements indicate the frequency of the call events processed by the switch. The other input/output (I/O) time used by the call processor to process messages not related to call processing is separated from the call processing I/O time. A relationship between the other I/O time and the sum of the call processing time and call processing I/O time is determined. A weighted average is determined from the summation of the products of: the frequency of events and the call processing time, the frequency of events and the call processing I/O time, and the other I/O time. The weighted average is then divided into the call processor occupancy time, in hours, to determine the switch capacity.

US Patent:

59074620, May 25, 1999

Filed:

Sep 7, 1994

Appl. No.:

8/302145

Inventors:

Amitava Chatterjee - Plano TX
Charvaka Duvvury - Plano TX
Ping Yang - Richardson TX
Ekanayake Ajith Amerasekera - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 900

US Classification:

361 56

Abstract:

A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).

US Patent:

61731757, Jan 9, 2001

Filed:

Oct 21, 1997

Appl. No.:

8/955201

Inventors:

Manar Alazma - Dallas TX
Eddy H. Trink - Plano TX
Ping Yang - Plano TX
Kalyan Basu - Plano TX

Assignee:

Nortel Networks Limited - Montreal

International Classification:

H04Q 720

US Classification:

455423

Abstract:

The provisioning process of the present invention first determines the average number of units of the system resource that are held per call. This parameter is a function of the call model and call-related event holding times. The average number of units is used, along with the Busy Hour Call Attempts to determine the holding rate, R. sub. resource, of that particular call-related event to be allocated memory. The holding rate is then used by. left brkt-top. R. sub. resource +7R. sub. resource. right brkt-top. to determine the number of resources required to be allocated to the call-related event.

US Patent:

50538489, Oct 1, 1991

Filed:

Dec 16, 1988

Appl. No.:

7/285440

Inventors:

Theodore W. Houston - Richardson TX
Ping Yang - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702

US Classification:

357 51

Abstract:

A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carriers caused by the particle will pass through the resistive area (88, 89) causing a voltage drop which will prevent the upset of the MOS circuit. A low resistance path is provided for the normal operating current in the device so that the normal operating parameters of the device are not affected by the protection provided by the resistive area (88, 89).

US Patent:

54651891, Nov 7, 1995

Filed:

Aug 12, 1994

Appl. No.:

8/289983

Inventors:

Thomas L. Polgreen - Dallas TX
Amitava Chatterjee - Garland TX
Ping Yang - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02H 904

US Classification:

361 58

Abstract:

A new semiconductor controlled rectifier which may be used to provide on-chip protection against ESD stress applied at the input, output, power supply pins or between any arbitrary pair of pins of an integrated circuit is disclosed. The structure which has the lowest breakdown voltage for a given technology is incorporated into the SCR enabling a SCR trigger voltage determined by the lowest breakdown-structure.

US Patent:

50198785, May 28, 1991

Filed:

Mar 31, 1989

Appl. No.:

7/332652

Inventors:

Ping Yang - Richardson TX
Amitava Chatterjee - Dallas TX
Shian Aur - Plano TX
Thomas L. Polgreen - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2910

US Classification:

357 233

Abstract:

A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V. sub. g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V. sub. PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.