Ping F Yeung

US Patent:

6609229, Aug 19, 2003

Filed:

Aug 9, 2000

Appl. No.:

09/635598

Inventors:

Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada, II - Los Altos CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Ping Fai Yeung - San Jose CA

Assignee:

O-In Design Automation, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 703 14, 703 17

Abstract:

A programmed computer generates descriptions of circuits (called âcheckersâ) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuits description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuits description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

US Patent:

6848088, Jan 25, 2005

Filed:

Jun 17, 2002

Appl. No.:

10/174379

Inventors:

Jeremy Rutledge Levitt - San Jose CA, US
Christophe Gauthron - Mountain View CA, US
Ping Fai Yeung - San Jose CA, US
Kalyana C. Mulam - San Jose CA, US
Ramesh Sathianathan - Sunnyvale CA, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F 1750
G06F 1710
G06F 760
G06F 945

US Classification:

716 4, 716 2, 703 2, 703 22

Abstract:

The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e. g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicated that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

US Patent:

6885983, Apr 26, 2005

Filed:

May 4, 2001

Appl. No.:

09/849005

Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul Il Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F017/50

US Classification:

703 14, 703 15, 703 16, 716 4

Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

US Patent:

7007249, Feb 28, 2006

Filed:

Jan 20, 2003

Appl. No.:

10/348116

Inventors:

Tai An Ly - Fremont CA, US
Jean-Charles Giomi - Menlo Park CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
David Lansing Dill - Redwood City CA, US
Paul II Estrada - Los Alto CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Robert Kristianto Mardjuki - Danville CA, US
Ping Fai Yeung - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 703 13, 703 20, 703 23, 703 28

Abstract:

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

US Patent:

7243322, Jul 10, 2007

Filed:

Jun 1, 2004

Appl. No.:

10/859055

Inventors:

Tai An Ly - San Jose CA, US
Ka Kei Kwok - Milpitas CA, US
Vijaya Vardhan Gupta - San Jose CA, US
Ross Andrew Ander - Los Altos CA, US
Ping Fai Yeung - San Jose CA, US
Neil Patrick Hand - Menlo Park CA, US

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 6

Abstract:

During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.

US Patent:

7318205, Jan 8, 2008

Filed:

Dec 6, 2004

Appl. No.:

11/006238

Inventors:

Jeremy Rutledge Levitt - San Jose CA, US
Christophe Gauthron - Mountain View CA, US
Ping Fai Yeung - San Jose CA, US
Kalyana C. Mulam - San Jose CA, US
Ramesh Sathianathan - Sunnyvale CA, US

International Classification:

G06F 17/50

US Classification:

716 4, 716 2

Abstract:

The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e. g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

US Patent:

7454324, Nov 18, 2008

Filed:

Jan 10, 2003

Appl. No.:

10/340500

Inventors:

James Andrew Garrard Seawright - Mountain View CA, US
Ramesh Sathianathan - Sunnyvale CA, US
Christophe G. Gauthron - Mountain View CA, US
Jeremy R. Levitt - San Jose CA, US
Kalyana C. Mulam - San Jose CA, US
Ping Fai Yeung - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

703 14, 716 2, 716 4, 716 5

Abstract:

A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called “primary criteria”) are applied, the selected states may be pruned by application of additional criteria (also called “secondary criteria”) prior to formal analysis.

US Patent:

7454728, Nov 18, 2008

Filed:

Jun 7, 2007

Appl. No.:

11/759888

Inventors:

Tai An Ly - San Jose CA, US
Ka Kei Kwok - Milpitas CA, US
Vijaya Vardhan Gupta - San Jose CA, US
Ross Andrew Andersen - Los Altos CA, US
Ping Fai Yeung - San Jose CA, US
Neil Patrick Hand - Menlo Park CA, US

International Classification:

G06F 17/50
G06F 9/45

US Classification:

716 5, 716 6

Abstract:

During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains (“CDC” signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.