Ping Kwong Yeung

US Patent:

6609229, Aug 19, 2003

Filed:

Aug 9, 2000

Appl. No.:

09/635598

Inventors:

Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada, II - Los Altos CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Ping Fai Yeung - San Jose CA

Assignee:

O-In Design Automation, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 703 14, 703 17

Abstract:

A programmed computer generates descriptions of circuits (called âcheckersâ) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuits description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuits description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

US Patent:

6885983, Apr 26, 2005

Filed:

May 4, 2001

Appl. No.:

09/849005

Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul Il Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F017/50

US Classification:

703 14, 703 15, 703 16, 716 4

Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

US Patent:

7007249, Feb 28, 2006

Filed:

Jan 20, 2003

Appl. No.:

10/348116

Inventors:

Tai An Ly - Fremont CA, US
Jean-Charles Giomi - Menlo Park CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
David Lansing Dill - Redwood City CA, US
Paul II Estrada - Los Alto CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Robert Kristianto Mardjuki - Danville CA, US
Ping Fai Yeung - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 703 13, 703 20, 703 23, 703 28

Abstract:

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

US Patent:

7478028, Jan 13, 2009

Filed:

Jan 12, 2005

Appl. No.:

11/035275

Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul II Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US

International Classification:

G06F 17/50

US Classification:

703 14, 703 15, 703 16, 716 4

Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

US Patent:

62927655, Sep 18, 2001

Filed:

Oct 20, 1997

Appl. No.:

8/954765

Inventors:

Robert Kristianto Mardjuki - Danville CA
David Lansing Dill - Redwood City CA
Jing Chyuarn Lin - Sunnyvale CA
Ping Fai Yeung - San Jose CA
Paul II Estrada - Los Alto CA
Jean-Charles Giomi - Menlo Park CA
Tai An Ly - Fremont CA
Kalyana C. Mulam - San Jose CA
Lawrence Curtis Widdoes - San Jose CA
Paul Andrew Wilcox - Palo Alto CA

Assignee:

O-In Design Automation - San Jose CA

International Classification:

G06F 1750

US Classification:

703 14

Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

US Patent:

61759465, Jan 16, 2001

Filed:

Oct 20, 1997

Appl. No.:

8/955329

Inventors:

Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada - Los Alto CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Lawrence Curtis Widdoes - San Jose CA
Ping Fai Yeung - San Jose CA

Assignee:

O-IN Design Automation - San Jose CA

International Classification:

G06F 1750
G06F 1650

US Classification:

716 4

Abstract:

A programmed computer generates descriptions of circuits (called "checkers") that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.