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Pranava Y Alekal

age ~40

from Seattle, WA

Pranava Alekal Phones & Addresses

  • Seattle, WA
  • 1914 SE Oak St APT 1, Portland, OR 97214
  • Hillsboro, OR
  • Lakewood, CA
  • Berkeley, CA

Work

  • Company:
    Intel corporation
    Jun 1, 2008
  • Position:
    Software engineer

Education

  • Degree:
    Bachelors, Bachelor of Science
  • School / High School:
    University of California, Berkeley
    2005 to 2007
  • Specialities:
    Electrical Engineering, Electrical Engineering and Computer Science, Computer Science

Skills

.Net • C# • Scrum • C++ • Software Engineering • Software Development • Linux • Perl • C • Unix

Industries

Computer Software

Resumes

Pranava Alekal Photo 1

Software Development Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Computer Software
Work:
Intel Corporation
Software Engineer

Amazon
Software Development Engineer
Education:
University of California, Berkeley 2005 - 2007
Bachelors, Bachelor of Science, Electrical Engineering, Electrical Engineering and Computer Science, Computer Science
Skills:
.Net
C#
Scrum
C++
Software Engineering
Software Development
Linux
Perl
C
Unix

Us Patents

  • Highly Configurable Power-Delivery Management Policy

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  • US Patent:
    20190227612, Jul 25, 2019
  • Filed:
    Mar 30, 2019
  • Appl. No.:
    16/370930
  • Inventors:
    Chee Lim Nge - Beaverton OR, US
    James Hermerding II - Vancouver WA, US
    Zhongsheng Wang - Portland OR, US
    Pranava Alekal - Portland OR, US
  • International Classification:
    G06F 1/3203
  • Abstract:
    Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.
  • On-The-Fly Performance Adjustment For Solid State Storage Devices

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  • US Patent:
    20140359196, Dec 4, 2014
  • Filed:
    Jun 27, 2013
  • Appl. No.:
    13/929708
  • Inventors:
    Daniel J. Ragland - Hillsboro OR, US
    Christopher E. Saleski - Portland OR, US
    Richard P. Mangold - Forest Grove OR, US
    Chun L. Yi - Richmond, CA
    Pranava Y. Alekal - Hillsboro OR, US
    Kevin Southern - Aloha OR, US
  • International Classification:
    G06F 12/00
  • US Classification:
    711102
  • Abstract:
    Methods and apparatus related to on-the-fly performance adjustment techniques for solid state storage devices are described. In one embodiment, a controller logic controls access to one or more non-volatile memory devices. The controller logic causes a change in an operational frequency of one or more of: the controller logic, a bus that couples the one or more non-volatile memory devices to the controller logic, and one or more of the one or more non-volatile memory devices. Also, the controller logic is capable of causing the change in the operational frequency in response to a command. Furthermore, changing power limits is made possible to scale solid state storage device performance based on system capabilities. Other embodiments are also disclosed and claimed.

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