Prashant D Parmar

US Patent:

20040245610, Dec 9, 2004

Filed:

Jun 4, 2003

Appl. No.:

10/455906

Inventors:

Dong Zhong - Chandler AZ, US
Jung Kang - Chandler AZ, US
Prashant Parmar - Gilbert AZ, US
Hyunjun Kim - Chandler AZ, US
Joel Auernheimer - Phoenix AZ, US

International Classification:

H01L023/02

US Classification:

257/678000

Abstract:

In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

US Patent:

20050068751, Mar 31, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/674886

Inventors:

Hyunjun Kim - Chandler AZ, US
Jiangqi He - Gilbert AZ, US
Yuan-Liang Li - Chandler AZ, US
Prashant Parmar - Gilbert AZ, US

International Classification:

H05K007/06

US Classification:

361780000, 174255000, 174262000, 361794000

Abstract:

According to some embodiments, a floating trace is provided on a signal layer (e.g., of a printed circuit board).

US Patent:

20190096798, Mar 28, 2019

Filed:

Sep 28, 2017

Appl. No.:

15/718012

Inventors:

- Santa Clara CA, US
Arnab Sarkar - Chandler AZ, US
Arghya Sain - Chandler AZ, US
Kristof Darmawikarta - Chandler AZ, US
Henning Braunisch - Phoenix AZ, US
Prashant D. Parmar - Gilbert AZ, US
Sujit Sharan - Chandler AZ, US
Johanna M. Swan - Scottsdale AZ, US
Feras Eid - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/50
H01L 21/48
H01L 23/498

Abstract:

Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.