Pratik N Mahajan
age ~39
from San Jose, CA
- Also known as:
-
- Mahajan Pratik
Pratik Mahajan Phones & Addresses
- San Jose, CA
- Beaverton, OR
- Santa Clara, CA
- 201 S 4Th St APT 603, San Jose, CA 95112
Work
-
Company:Invensense, inc.May 2013
-
Position:Senior verification engineer
Education
-
Degree:Master of Science
-
School / High School:San Jose State University2008 to 2010
-
Specialities:Electrical Engineering; Digital Design
Skills
Verilog • Perl • Embedded Systems • Fpga • Vlsi • Asic • C • Systemverilog • Debugging • Arm • Integrated Circuit Design • Logic Synthesis • Cadence Virtuoso • Rtl Design
Interests
Linux (User Space) • Embedded Systems • Asic • Soc • Verilog • System Verilog
Industries
Semiconductors
Resumes
Senior Verification Engineer At Invensense, Inc
view sourceLocation:
190 Ryland St, San Jose, CA 95110
Industry:
Semiconductors
Work:
InvenSense, Inc. since May 2013
Senior Verification Engineer
InvenSense, Inc. - Sunnyvale, CA Oct 2012 - May 2013
Verification Engineer
Blue Pearl Software - Santa Clara Apr 2011 - Sep 2012
Application Engineer
San Jose State University Aug 2010 - Dec 2010
ISA - Instructional Student Assistant
SJSU Jul 2008 - Dec 2010
Student
Senior Verification Engineer
InvenSense, Inc. - Sunnyvale, CA Oct 2012 - May 2013
Verification Engineer
Blue Pearl Software - Santa Clara Apr 2011 - Sep 2012
Application Engineer
San Jose State University Aug 2010 - Dec 2010
ISA - Instructional Student Assistant
SJSU Jul 2008 - Dec 2010
Student
Education:
San Jose State University 2008 - 2010
Master of Science, Electrical Engineering; Digital Design UTL 2007 - 2008
Diploma in Embedded Systems, Embedded Systems University of Pune 2002 - 2006
Bachelor of Engineering, Electronics Engineering
Master of Science, Electrical Engineering; Digital Design UTL 2007 - 2008
Diploma in Embedded Systems, Embedded Systems University of Pune 2002 - 2006
Bachelor of Engineering, Electronics Engineering
Skills:
Verilog
Perl
Embedded Systems
Fpga
Vlsi
Asic
C
Systemverilog
Debugging
Arm
Integrated Circuit Design
Logic Synthesis
Cadence Virtuoso
Rtl Design
Perl
Embedded Systems
Fpga
Vlsi
Asic
C
Systemverilog
Debugging
Arm
Integrated Circuit Design
Logic Synthesis
Cadence Virtuoso
Rtl Design
Interests:
Linux (User Space)
Embedded Systems
Asic
Soc
Verilog
System Verilog
Embedded Systems
Asic
Soc
Verilog
System Verilog
Pratik Mahajan San Jose, CA
view sourceWork:
Blue Pearl Software, Inc.
Apr 2011 to 2000
Application Engineer, San Jose State University
San Jose, CA
Aug 2008 to Dec 2010
ASIC Engineer (Student) Literacy Bridge
San Jose, CA
Nov 2008 to Feb 2009
Embedded Engineer (Volunteer) Wifi-Soft Sol. Pvt. Ltd
Pune, Maharashtra
Aug 2007 to Oct 2008
Embedded Engineer
Apr 2011 to 2000
Application Engineer, San Jose State University
San Jose, CA
Aug 2008 to Dec 2010
ASIC Engineer (Student) Literacy Bridge
San Jose, CA
Nov 2008 to Feb 2009
Embedded Engineer (Volunteer) Wifi-Soft Sol. Pvt. Ltd
Pune, Maharashtra
Aug 2007 to Oct 2008
Embedded Engineer
Education:
San Jose State University
San Jose, CA
Jan 2008 to Jan 2010
MSEE in Digital Logic Design (ASIC) UTL Technologies
Jan 2007 to Jan 2007
Diploma in Embedded Systems V.I.T. Pune University B.E.E.E
Aug 2006 UCSC [Extension]
Santa Clara, CA
2012
Advance Verification with SystemVerilog
San Jose, CA
Jan 2008 to Jan 2010
MSEE in Digital Logic Design (ASIC) UTL Technologies
Jan 2007 to Jan 2007
Diploma in Embedded Systems V.I.T. Pune University B.E.E.E
Aug 2006 UCSC [Extension]
Santa Clara, CA
2012
Advance Verification with SystemVerilog
Skills:
ASIC Design, ASIC Verification, Embedded Systems
Pratik Mahajan Santa Clara, CA
view sourceWork:
San Jose State University
San Jose, CA
Aug 2008 to Dec 2010
ASIC Design Engineer (Student) Literacy Bridge
San Jose, CA
Nov 2008 to Feb 2009
Embedded Engineer Wifi-Soft Sol. Pvt. Ltd
Pune, Maharashtra
Aug 2007 to Oct 2008
Embedded Engineer
San Jose, CA
Aug 2008 to Dec 2010
ASIC Design Engineer (Student) Literacy Bridge
San Jose, CA
Nov 2008 to Feb 2009
Embedded Engineer Wifi-Soft Sol. Pvt. Ltd
Pune, Maharashtra
Aug 2007 to Oct 2008
Embedded Engineer
Education:
San Jose State University
San Jose, CA
Jan 2008 to Jan 2010
MS in Electrical Engineering UTL Teechnologies
Pune, Maharashtra
Jan 2007 to Jan 2007
Diploma in Embedded Systems V.I.T. Pune University
Pune, Maharashtra
Jan 2002 to Jan 2006
BE in Electronics Engineering
San Jose, CA
Jan 2008 to Jan 2010
MS in Electrical Engineering UTL Teechnologies
Pune, Maharashtra
Jan 2007 to Jan 2007
Diploma in Embedded Systems V.I.T. Pune University
Pune, Maharashtra
Jan 2002 to Jan 2006
BE in Electronics Engineering
Skills:
RTL Synthesis, HDL Design, RTL Design, Debug, Verification, Gate Level Simulation, Scripting, ASIC Design, Verilog, System Verilog, Perl, Bash, C, Assembly language. Hardware Design, Digital Design
Us Patents
-
Efficient Mechanism Of Fault Qualification Using Formal Verification
view source -
US Patent:20180349521, Dec 6, 2018
-
Filed:Jun 1, 2018
-
Appl. No.:15/996307
-
Inventors:- Mountain View CA, US
Arunava Saha - Sunnyvale CA, US
Pratik Mahajan - Cupertino CA, US
Per Bjesse - Portland OR, US
Alfred Koelbl - Hillsboro OR, US -
International Classification:G06F 17/50
-
Abstract:The fault analysis problem is modelled by automatically creating additional properties (fault properties) and constraints based on the injected faults and the existing user assertions. These fault properties and constraints are sent to formal verification in a single run to qualify all of the faults together, rather than sequentially checking each fault in a separate formal verification run.
Pratik Mahajan
view source
Pratik Mahajan
view source
Pratik Mahajan
view source
Pratik Mahajan
view source
Pratik Mahajan
view source
Pratik Mahajan
view source
Pratik Mahajan
view source
Pratik Mahajan
view sourceMyspace
Googleplus
Pratik Mahajan
Education:
Symbiosis Institute of Media and Communication (UG) - Media Studies
About:
I go with the wind. I am a silent observer, a tresspasser, a walker, a do-er, a Traveller.
Bragging Rights:
Nothing.
Pratik Mahajan
Education:
NSESK, KBPIMSR - Administration, SCOEM - HR and Marketing
Pratik Mahajan
Education:
S. K. Somaiya College of Engineering - Commerce, Swami Vivekanand Vidyamandir, Dattanagar
Pratik Mahajan
Work:
I am student
Pratik Mahajan
About:
If you ever start taking things too seriously, Just remember that we are talking monkeys on an organic spaceship flying through the Universe. -- Joe Rogan :D
Pratik Mahajan
Pratik Mahajan
Pratik Mahajan
Youtube
Get Report for Pratik N Mahajan from San Jose, CA, age ~39