Pravin M Patel

US Patent:

7760006, Jul 20, 2010

Filed:

May 8, 2008

Appl. No.:

12/117435

Inventors:

Kevin P. Lavery - Sugar Land TX, US
Jim D. Childers - Missouri City TX, US
Pravin P. Patel - Sugar Land TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 17/16
H03K 19/003

US Classification:

327391, 327384, 327112, 327170, 326 9, 326 15, 326 82, 326 83

Abstract:

Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

US Patent:

20080277727, Nov 13, 2008

Filed:

Sep 21, 2007

Appl. No.:

11/903427

Inventors:

Pravin P. Patel - Sugar Land TX, US
Roger A. Cline - Plano TX, US
Steven G. Howard - Plano TX, US
Robert C. Choens - Houston TX, US

International Classification:

H01L 23/62

US Classification:

257355, 257E23001

Abstract:

An electrostatic protection circuit has a transistor for pumping charge into the substrate and a transistor, including a parasitic transistor, for removing charge from the substrate and tabs. The circuit is enclosed by barrier that prevents the migration of charge from the region of the transistors. The added charge in the region of the parasitic transistor, resulting from the increased charge in the region of the parasitic transistor, increases the flow of current between electrodes of the transistor, thereby removing the electrostatic charge more efficiently. removing the electrostatic charge more efficiently.

US Patent:

20130049884, Feb 28, 2013

Filed:

Aug 22, 2011

Appl. No.:

13/214749

Inventors:

Kevin Patrick Lavery - Sugar Land TX, US
Pravin P. Patel - Sugar Land TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H03H 7/00

US Classification:

333172, 333167

Abstract:

Low-frequency digital data input signals in an integrated circuit are controlled between first and second stages in a signal input path of the integrated circuit by a capacitance in the signal input path between the first and second stages. The capacitance is sized to attenuate high-frequency noise in the signal input path. In one embodiment, the integrated circuit may be an input buffer circuit in which the capacitance is a capacitor between the signal input path and a reference potential, a voltage source, or both. In another embodiment, the integrated circuit may be an oscillator circuit in which the capacitance is provided between corresponding elements of a differential pair of transistors in the first stage.

US Patent:

49012800, Feb 13, 1990

Filed:

Apr 19, 1989

Appl. No.:

7/342584

Inventors:

Pravin Patel - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

36518911

Abstract:

A circuit for assisting the charging of a line conductor having a distributed resistance and capacitance, such as a word line in a semiconductor memory device, is disclosed. In the conventional memory device, a driver circuit is disposed at one end of a word line, with a circuit for holding unselected word lines at the discharged voltage being disposed at the end of the word line opposite from the drive circuit. The invention is directed towards a pull-up circuit being disposed at the end of the word line opposite the driver circuit, the pull-up circuit having a transistor which is precharged to a high voltage prior to the active cycle. The precharged transistor is discharged as the selected word line is charged by the driver circuit, causing a driving node in the circuit to be connected to a high supply voltage. The driving node is connected to the word line by a transistor which is responsive to a select signal generated by the address decoder; once selected, the word line at the end opposite the driver circuit is driven by the high supply voltage. This will enable the selected word line to be pulled up to the high supply voltage at both ends, thereby reducing the time required to charge the word line to the required voltage level.

US Patent:

48766712, Oct 24, 1989

Filed:

Apr 6, 1989

Appl. No.:

7/336637

Inventors:

Roger D. Norwood - Sugar Land TX
Jino Chun - Houston TX
Pravin P. Patel - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 800
G11C 700

US Classification:

365233

Abstract:

A semiconductor dynamic memory device is disclosed which contains circuitry for implementing both page mode and nibble modes using a conductor level selection. A clock voltage used in column decoding and output is either coupled to or decoupled from the column strobe or CAS input by conductor, so this clock voltage is rendered either dependent on, or independent of, the cycling of the column strobe.

US Patent:

50016733, Mar 19, 1991

Filed:

Aug 14, 1989

Appl. No.:

7/393332

Inventors:

Roger D. Norwood - Sugar Land
Jino Chun - Houston
Pravin P. Patel - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 800
G11C 700

US Classification:

365233

Abstract:

A semiconductor dynamic memory device contains circuitry for implementing either page mode or nibble mode access using a selected conductor connection. A clock voltage used in column decoding and outputting is coupled either from the column strobe or the CAS input by a conductor so that the clock voltage is rendered either dependent upon or independent from the cycling of the column strobe.

US Patent:

46850899, Aug 4, 1987

Filed:

Aug 29, 1984

Appl. No.:

6/645579

Inventors:

Pravin P. Patel - Sugar Land TX
Roger D. Norwood - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1140

US Classification:

365233

Abstract:

A semiconductor dynamic memory device has an array of one-transistor cells, with row and column decode to produce a 4-bit wide input or output from the array. Single-bit data-in and data-out terminals for the device are coupled to the 4-bit array input/output in a sequential mode. The row and column addresses are latched when RAS and CAS drop, and the latched address includes the address of the starting bit within the 4-bit sequence for serial I/O. The other three bits follow as CAS is cycled. This starting address is used to set a bit in a 4-bit ring counter, which is then used to cycle through the sequence. To reduce power dissipation, the inverter stages of the ring counter are operated by pulsed clocks generated from the asynchronous memory control clocks received from the CPU.

US Patent:

20060170473, Aug 3, 2006

Filed:

Jan 31, 2006

Appl. No.:

11/344323

Inventors:

Jim Childers - Missouri City TX, US
Pravin Patel - Sugarland TX, US

International Classification:

H03K 5/12

US Classification:

327170000

Abstract:

A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET falls below its turn-on voltage threshold, and turning ON the N-channel FET until the voltage on the gate of the P-channel FET falls below its turn-on voltage threshold.