Qazi A Mahmood from 3169 Apperson Ridge Dr, San Jose, CA 95148, age 75, Phone: (408)2384752

Wikipedia

Qazi Syed Inayatullah

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Shaikh Mohammad was earlier married to Raj Bibi, daughter of Qazi Ibrahim of Tijara. Qazi Ibrahim was the son of Qazi Mahmood. The son of Qazi Ibrahim, Qazi ...

Resumes

Marketing And Engineering Consultant

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Location:

San Francisco, CA

Industry:

Semiconductors

Work:

Intilop
Marketing and Engineering Consultant
Promatch 2010 - 2011
Volunteer Team Co-Lead and Workshop Facilitator of Training and Development at Career Resource Center
Chartered Semiconductor 2004 - 2009
Senior Manager Field Engineering
Intelop 2004 - 2004
Asic Design Consultant
Fujitsu 1998 - 2002
Project Engineering Manager

Education:

Bangladesh University of Engineering and Technology
Bachelors, Bachelor of Science, Electrical Engineering Mississippi State University
Master of Science, Masters, Electrical Engineering University of Phoenix
Master of Business Administration, Masters

Us Patents

Input Buffer Circuit Including An Input Level Translator With Sleep Function
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US Patent:

56024967, Feb 11, 1997
Filed:

May 23, 1996
Appl. No.:

8/652888
Inventors:

Qazi Mahmood - San Jose CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H03K 190185
H03K 3295
H03K 190948
US Classification:

326 71
Abstract:

An input buffer circuit is disclosed which provides better noise margin and sharper switching edges than previously known systems. This circuit includes an input level translator, a Schmitt trigger circuit coupled to the input level translator circuit, a buffer, and sleep function circuit. The sleep function circuit reduces power when the input buffer circuit is powered down. The Schmitt trigger circuit comprises the hysteresis transfer characteristic providing means of the present invention. The Schmitt trigger circuit and buffer circuit, both with properly matched beta values for the participating transistors, allows for improved noise immunity of and sharper switching edges for the input buffer of the present invention.

Negative Feedback To Reduce Voltage Oscillation In Cmos Output Buffers
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US Patent:

54732638, Dec 5, 1995
Filed:

Dec 19, 1994
Appl. No.:

8/359235
Inventors:

Qazi Mahmood - San Jose CA
Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:

H03K 1716
US Classification:

326 27
Abstract:

A CMOS output buffer circuit includes negative feedback means for significantly reducing voltage oscillation. The buffer circuit is comprised of a pull-up transistor (P1), a pull-down transistor (N1), a first reference voltage generator circuit (44), a second reference voltage generator circuit (54), a first negative feedback circuit (48), and a second negative feedback circuit (58). First and second negative feedback circuits are coupled between the internal power supply potential/ground potential nodes and the gates of the pull-up/pull-down driver transistors so as to reduce the rate of change of the transient charging/discharging currents, respectively.