Qian Wu

US Patent:

8078833, Dec 13, 2011

Filed:

May 29, 2008

Appl. No.:

12/156006

Inventors:

Xiaolin Wang - Concord MA, US
Qian Wu - San Jose CA, US
Benjamin Marshall - Stow MA, US
Fugui Wang - Sterling MA, US
Ke Ning - Framingham MA, US
Gregory Pitarys - Stow MA, US

Assignee:

Axis Semiconductor, Inc. - Boxborough MA

International Classification:

G06F 15/00
G06F 15/76

US Classification:

712 15, 712229

Abstract:

The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

US Patent:

8181003, May 15, 2012

Filed:

May 29, 2008

Appl. No.:

12/156007

Inventors:

Xiaolin Wang - Concord MA, US
Qian Wu - San Jose CA, US
Benjamin Marshall - Stow MA, US
Fugui Wang - Sterling MA, US
Gregory Pitarys - Stow MA, US
Ke Ning - Framingham MA, US

Assignee:

Axis Semiconductor, Inc. - Boxborough MA

International Classification:

G06F 9/30

US Classification:

712225, 712 11, 712220

Abstract:

Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

US Patent:

20130138919, May 30, 2013

Filed:

Oct 23, 2012

Appl. No.:

13/658141

Inventors:

Axis Semiconductor, Inc. - Boxborough MA, US
Qian Wu - Redwood City CA, US
Ben Marshall - Stow MA, US
John Eppling - Acton MA, US
Jie Sun - Sudbury MA, US

Assignee:

AXIS SEMICONDUCTOR, INC. - Boxborough MA

International Classification:

G06F 15/76

US Classification:

712 29, 712E09003

Abstract:

A multi-core processor includes a tree-like structure having a plurality of computing cores arranged in hierarchical levels, the cores all having the same logical architecture. Each core can include computing, interconnecting, and/or storage elements. The functionality of an individual element can be supplied by an entire core in a lower level. A method for programming the processor includes hierarchically decomposing an application into interconnected sub-functions, mapping the sub-functions onto groups of cores at appropriate levels of the processor, and interconnecting the mapped sub-functions so as to hierarchically compose the complete application. Sub-functions can be sequential, concurrent, and/or pipelined. Interconnections can be static or dynamically switchable under program control. Interconnect elements can also be used to implement flow control as needed in pipelined operations to maintain data coherency. The decomposing and mapping process can be iterated on sub-functions so as to optimize load balancing, software performance, and hardware efficiency.

US Patent:

20180143834, May 24, 2018

Filed:

Jan 22, 2018

Appl. No.:

15/876696

Inventors:

Xiaolin Wang - Methuen MA, US
Qian Wu - Redwood City CA, US

International Classification:

G06F 9/30
H04B 1/00
G06F 17/50
G06F 9/455
G06F 15/78
G06F 15/76

Abstract:

A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.

US Patent:

20170300333, Oct 19, 2017

Filed:

Apr 17, 2017

Appl. No.:

15/488672

Inventors:

Xiaolin Wang - Methuen MA, US
Qian Wu - Redwood City CA, US

International Classification:

G06F 9/30
G06F 17/50
G06F 15/78
G06F 15/76
H04B 1/00
G06F 9/455
G06F 15/76

Abstract:

A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module. In embodiments, a Time Field is added to the instruction format for all programming units that specifies the number of clock cycles for which only one instruction fetch and decode will be performed.