Qiang X Chen

US Patent:

6391643, May 21, 2002

Filed:

Oct 27, 1999

Appl. No.:

09/428587

Inventors:

Qiang Chen - Sunnyvale CA
David M. Liu - Los Altos CA
Brian S. Kersten - San Mateo CA
Christine M. Wu - Fremont CA

Assignee:

Cygnus, Inc. - Redwood City CA

International Classification:

G01N 3100

US Classification:

436 14, 436 8, 422 61, 435 14, 73 101, 73 102, 600347, 600365, 604 20

Abstract:

An automated system for continual transdermal extraction of analytes present in a biological system is described. The system optionally uses reverse iontophoresis to carry out the continual transdermal extraction of the analytes. The present invention describes quality control test kits, and methods of use thereof, for testing the ability of the system to provide reliable, effective, and accurate determination of analyte concentration.

US Patent:

7531403, May 12, 2009

Filed:

Oct 2, 2006

Appl. No.:

11/538001

Inventors:

Ali Icel - Cupertino CA, US
Qiang Chen - Sunnyvale CA, US
Mario M. Pelella - Mountain View CA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 21/8238

US Classification:

438201, 438199, 257E21545

Abstract:

SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.

US Patent:

7761823, Jul 20, 2010

Filed:

May 15, 2007

Appl. No.:

11/803646

Inventors:

Jung-Suk Goo - Los Altos CA, US
Qiang Chen - Sunnyvale CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 4

Abstract:

According to one exemplary embodiment, a method for adjusting a transistor model for increased circuit simulation accuracy includes determining a first gate CD offset by matching a C-V test structure having a normalized channel current to an I-V test structure having the normalized channel current. The method further includes utilizing the first gate CD offset to adjust the transistor model for increased circuit simulation. The method also includes determining a second gate CD offset by varying I-V and C-V gate length parameters in the transistor model to cause simulated data from a test circuit to be approximately equal to measured data from the test circuit. The method further includes utilizing the second gate CD offset to adjust the transistor model.

US Patent:

7880229, Feb 1, 2011

Filed:

Oct 18, 2007

Appl. No.:

11/874454

Inventors:

Sriram Madhavan - Santa Clara CA, US
Qiang Chen - Cupertino CA, US
Darin A. Chan - Campbell CA, US
Jung-Suk Goo - Los Altos CA, US

Assignee:

GlobalFoundries Inc. - Grand Cayman

International Classification:

H01L 27/12

US Classification:

257347, 257E27111, 257E21631

Abstract:

A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

US Patent:

7986008, Jul 26, 2011

Filed:

Mar 27, 2009

Appl. No.:

12/413185

Inventors:

Ali Icel - Cupertino CA, US
Qiang Chen - Sunnyvale CA, US
Mario M. Pelella - Mountain View CA, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

H01L 27/12

US Classification:

257351, 438153

Abstract:

SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of a first conductivity type and first doping concentration in the first semiconductor layer. A channel region of a second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of the first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of the first conductivity determining dopant.

US Patent:

8271931, Sep 18, 2012

Filed:

Apr 30, 2010

Appl. No.:

12/771754

Inventors:

Qiang Chen - Cupertino CA, US
Sridhar Tirumala - Saratoga CA, US
Akash Jain - Milpitas CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716133, 716132, 716136, 703 2

Abstract:

A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results.

US Patent:

8293606, Oct 23, 2012

Filed:

Dec 20, 2010

Appl. No.:

12/973377

Inventors:

Sriram Madhavan - Santa Clara CA, US
Qiang Chen - Cupertino CA, US
Darin A. Chan - Campbell CA, US
Jung-Suk Goo - Los Altos CA, US

Assignee:

GLOBALFOUNDARIES, Inc. - Grand Cayman

International Classification:

H01L 27/12

US Classification:

438278, 438 17, 438 18, 257E27111, 257E21631

Abstract:

A body tie test structure and methods for its manufacture are provided. The transistor comprises a body-tied semiconductor on insulator (SOI) transistor formed in a layer of semiconductor material, the transistor comprising a cross-shaped gate structure with a substantially constant gate length L. An insulating blocking layer enables formation of a spacer region in the layer of semiconductor material separating the source and drain regions from the body tie region. A conductive channel with substantially the same inversion characteristics as the intrinsic transistor body connects the body tie to the intrinsic transistor body through the spacer region.

US Patent:

8359558, Jan 22, 2013

Filed:

Mar 16, 2010

Appl. No.:

12/724955

Inventors:

Qiang Chen - Cupertino CA, US
Sridhar Tirumala - Saratoga CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716106, 716100, 716108, 716113, 716122, 716132, 716133, 716134, 716136, 716139

Abstract:

An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.