Qing H Yang

US Patent:

7177887, Feb 13, 2007

Filed:

Sep 10, 2003

Appl. No.:

10/659127

Inventors:

Qing Yang - Saunderstown RI, US
Jian Li - Ithaca NY, US

International Classification:

G06F 17/00

US Classification:

707204, 707201

Abstract:

A remote online information back-up comprises a local computing system and a remote computing system. The local computing system includes a local disk and a local device driver. The local device driver is responsive to requests from a local application executing on the local computing system, for selectively processing calls to the local disk or to a remote disk for backup of data resident on the local disk. The remote computing system includes the remote disk and a remote device driver. The remote device driver is responsive to calls from either the local device driver or calls from a remote application executing on the remote computing system, wherein calls from the local device driver are processed to perform backup operations to the remote disk of data resident on the local computing system.

US Patent:

7275134, Sep 25, 2007

Filed:

Feb 17, 2004

Appl. No.:

10/780108

Inventors:

Qing Yang - Saunderstown RI, US
Xubin He - Cookeville TN, US

Assignee:

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI

International Classification:

G06F 12/00

US Classification:

711122, 711135, 710 53

Abstract:

A SCSI-to-IP cache storage system interconnects a host computing device or a storage unit to a switched packet network. The cache storage system includes a SCSI interface () that facilitates system communications with a host computing device or the storage unit, and an Ethernet interface () that allows the system to receive data from and send data to the Internet. The cache storage system further comprises a processing unit () that includes a processor (), a memory () and a log disk () configured as a sequential access device. The log disk () caches data along with the memory () resident in the processing unit (), wherein the log disk () and the memory () are configured as a two-level hierarchical cache.

US Patent:

7730347, Jun 1, 2010

Filed:

May 17, 2007

Appl. No.:

11/749901

Inventors:

Qing K. Yang - Saunderstown RI, US

Assignee:

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI

International Classification:

G06F 11/00

US Classification:

714 6, 714 15, 714 20

Abstract:

A storage architecture is disclosed for maintaining data in the event of data storage failure. The storage architecture includes a plurality of disks in a redundant disk array, a time-recovery disk, and an encoder system. Each of the plurality of disks in the redundant disk array includes a parity output bit that provides an indication of the parity of the data in each respective disk. The time-recovery disk is in communication with at least one of the redundant disk arrays. The encoder system is coupled to the parity output bit of the at least one of the disks and is coupled to the time-recovery disk for providing encoding data regarding whether a block of data in the at least one disk has been changed.

US Patent:

7953926, May 31, 2011

Filed:

Sep 18, 2007

Appl. No.:

11/857319

Inventors:

Qing Yang - Saunderstown RI, US
Xubin He - Cookeville TN, US

Assignee:

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI

International Classification:

G06F 13/00

US Classification:

711113, 711122, 709217

Abstract:

A SCSI-to-IP cache storage system interconnects a host computing device or a storage unit to a switched packet network. The cache storage system includes a SCSI interface () that facilitates system communications with a host computing device or the storage unit, and a Ethernet interface () that allows the system to receive data from and send data to the Internet. The cache storage system further comprises a processing unit () that includes a processor (), a memory () and a log disk () configured as a sequential access device. The log disk () caches data along with the memory () resident in the processing unit (), wherein the log disk () and the memory () are configured as a two-level hierarchical cache.

US Patent:

7966452, Jun 21, 2011

Filed:

Jan 22, 2008

Appl. No.:

12/017479

Inventors:

Qing Yang - Saunderstown RI, US

Assignee:

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI

International Classification:

G06F 12/00

US Classification:

711118, 711126, 711E12062

Abstract:

A cache memory processing system is disclosed that is coupled to a main memory and a processing unit. The cache memory processing system includes an input, a low order bit data path, a high order bit data path and an output. The input is for receiving input data that includes at least one low order input bit and at least one high order input bit. The low order bit data path is for processing the at least one low order input bit and providing at least one low order output bit. The high order bit data path for processing the at least one high order input bit and providing at least one high order output bit. The high order bit data path includes at least one exclusive or gate. The output is for providing the at least one low order output bit and the at least one high order output bit.

US Patent:

8140772, Mar 20, 2012

Filed:

Oct 31, 2008

Appl. No.:

12/262260

Inventors:

Qing K. Yang - Saunderstown RI, US

Assignee:

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI

International Classification:

G06F 15/167
G06F 12/00

US Classification:

711141, 709216, 711112, 711162

Abstract:

A system and method are disclosed for maintaining a plurality of data storages coherent with one another for redundancy purposes. The system includes a first data storage system and a second data storage system. The first data storage system is coupled to a first transaction processor for handling input and output transactions, and is coupled to a wide area network. The second data storage system is coupled to a second transaction processor for handling input and output transactions, and is coupled to the wide area network. The first transaction processor permits a first data write transaction to occur with respect to data within the first data storage system, and the second transaction processor permits a second data write transaction to occur with respect to data within the second data storage system. The first transaction processor permits the second data write transaction to occur with respect to data within the first data storage system only upon data consistency between the first and second data storage systems being validated. The second transaction processor permits the first data write transaction to occur with respect to data within the second data storage system only upon data consistency between the first and second data storage systems being validated.

US Patent:

8153043, Apr 10, 2012

Filed:

Sep 21, 2011

Appl. No.:

13/238348

Inventors:

Rajendra K. Krishnaswamy - Lexington MA, US
Qing Yang - Bartlesville OK, US

Assignee:

Chevron Phillips Chemical Company LP - The Woodlands

International Classification:

B28B 3/20
B29C 47/00
C08L 23/08
C08L 23/00

US Classification:

2641761, 26417714, 524240, 524191, 526111

Abstract:

The present invention provides bimodal polyethylene resins in which the high molecular weight ethylene copolymer component typically has a relatively narrow molecular weight distribution, with short chain branching content being substantially constant across its molecular weight distribution. The resins of this invention are typically characterized by improved toughness and resistance to slow crack propagation properties making them useful for pressure pipe applications.

US Patent:

8239706, Aug 7, 2012

Filed:

Apr 20, 2010

Appl. No.:

12/763591

Inventors:

Qing K. Yang - Saunderstown RI, US

Assignee:

Board of Governors for Higher Education, State of Rhode Island and Providence Plantations - Providence RI

International Classification:

G06F 11/00

US Classification:

714 624, 714 15, 714 20

Abstract:

A method is disclosed of maintaining data. The method includes the steps of providing a plurality of data storage mediums, each comprising a parity bit that provides an indication of the parity of the data in each respective data storage medium, at least one of the data storage mediums providing an exclusive OR function of a parity output bit of the at least one of the plurality of data storage mediums; encoding data provided by the exclusive OR functionality of the parity output bit to provide encoded data; time stamping the encoded data with a time stamp circuit that is coupled to the encoded data to provide time stamped encoded data; and providing the time stamped encoded data to a time-retrieval data storage medium.