Qingda Lu

US Patent:

20220382760, Dec 1, 2022

Filed:

Jun 1, 2021

Appl. No.:

17/336047

Inventors:

- Singapore, SG
Qingda Lu - Bellevue WA, US
Shuo Chen - Bellevue WA, US
Yikang Xu - Redmond WA, US
Jiesheng Wu - Redmond WA, US
Rui Wang - Redmond WA, US

International Classification:

G06F 16/2455
G06F 16/23
G06F 16/25
G06F 16/22
G06F 16/18

Abstract:

A key-value store is provided, implementing multiple-tiered sorted data structures in memory and storage, including concurrent write buffers in memory, and page-level consolidation of updates on storage, where pages are trivially translated in physical-to-virtual address mapping. The key-value store is built on an indexed sorted data structure on storage, occupying much less storage space and incurring much less disk activity in consolidating updates than a conventional log-structured merge tree organized into files. Concurrent write buffers operate concurrently and independently so that data is committed from memory to storage in an efficient manner, while maintaining chronological sequence of delta pages. Trivial mapping allows mappings of a number of physical pages to be omitted, enabling page mapping tables to occupy less storage space, and simplifying processing workload of read operation retrievals from storage.

US Patent:

20170249008, Aug 31, 2017

Filed:

Oct 3, 2016

Appl. No.:

15/284377

Inventors:

- SANTA CLARA CA, US
ANIL AGGARWAL - PORTLAND OR, US
QINGDA LU - PORTLAND OR, US
RAHUL SETH - HILLSBORO OR, US
MICHAEL C. WALZ - HILLSBORO OR, US

Assignee:

INTEL CORPORATION - SANTA CLARA CA

International Classification:

G06F 1/32
G06F 13/24

Abstract:

Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.

US Patent:

20150095676, Apr 2, 2015

Filed:

Sep 27, 2013

Appl. No.:

14/040118

Inventors:

LEENA K. PUTHIYEDATH - Beaverton OR, US
ANIL AGGARWAL - Portland OR, US
QINGDA LU - Portland OR, US
RAHUL SETH - Hillsboro OR, US
MICHAEL C. WALZ - VANCOUVER WA, US

International Classification:

G06F 1/32

US Classification:

713323

Abstract:

Various embodiments are generally directed to an apparatus, method and other techniques for initiating a transition into a lower power state, determining that a device process prevents a platform processing device from completing the transition to the lower power state and interrupting a processing component from an intermediate power state in order to process the process prior to execution of a defined event.