Qingming S Shu

US Patent:

20050226079, Oct 13, 2005

Filed:

Aug 26, 2004

Appl. No.:

10/928504

Inventors:

Yiming Zhu - Belmont CA, US
Qingming Shu - Milpitas CA, US

International Classification:

G11C007/00

US Classification:

365230030

Abstract:

Memory methods and apparatuses providing for refresh and bandwidth enhancements for a dual-port memory array (e.g. a DRAM memory array) with balanced read and write timing specifications are disclosed. A port allocation for dual-port memory cell is adopted such that one port is assigned and shared for both read and refresh and the other port is assigned for write only. Double bandwidth is achieved by overlapping simultaneous read or refresh and write port access during the same cycle. No external refresh command is required and external accesses (reads and writes) are not interrupted or delayed under any circumstance. A high-speed SRAM compatible device can be fabricated from a dual-port DRAM or 3-Transistor cells or 2-Transistors and 1 capacitor cells. The preferred embodiments include a multi-bank dual-port memory array and a look-up-table logic which records the accessed word address and generates hit logic and idle cycles when a refresh stall is asserted by a refresh-jammed bank. A dual-port memory data lodge which temporarily detours the data flow is provided to store the data flow and to allow for refresh to occur in the refresh-jammed bank. Each of dual-port DRAM banks has its independent read, write and refresh decoder control. Therefore, simultaneous refresh and read-write operations are allowed in different banks. The size of data lodge is determined by guaranteeing that the refresh operations can be executed without pausing ongoing indefinite read and write operations.