Quang Thanh Le

US Patent:

7165144, Jan 16, 2007

Filed:

Mar 19, 2004

Appl. No.:

10/805105

Inventors:

Ashish V. Choubal - Austin TX, US
Christopher T. Foulds - Austin TX, US
Madhu R. Gumma - Austin TX, US
Quang T. Le - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711118, 711138, 711144, 711145, 711154

Abstract:

Provided are a method, system, and program for managing Input/Output (I/O) requests in a cache memory system. A request is received to data at a memory address in a first memory device, wherein data in the first memory device is cached in a second memory device. A determination is made as to whether to fetch the requested data from the first memory device to cache in the second memory device in response to determining that the requested data is not in the second memory device. The requested data in the first memory device is accessed and the second memory device is bypassed to execute the request in response to determining not to fetch the requested data from the first memory device to cache in the second memory device.

US Patent:

7516237, Apr 7, 2009

Filed:

Aug 20, 2003

Appl. No.:

10/645045

Inventors:

Bradley J. Booth - Austin TX, US
Quang Le - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/16
H04J 3/16

US Classification:

709232, 709250, 370465

Abstract:

Described are a device and system to transmit data to or receive data from one or more data lane interfaces. Each data lane interface may be capable of transmitting a serial data signal to or receiving a serial data signal from a data lane in a device-to-device interconnection. An effective data rate may be varied based, at least in part, upon a number of the data lane interfaces actively transmitting a serial data signal to or receiving a serial data signal from the device-to-device interconnection.

US Patent:

7573821, Aug 11, 2009

Filed:

Aug 17, 2005

Appl. No.:

11/206576

Inventors:

Murali Chilukoor - Bangalore Pin, IN
Quang Le - Austin TX, US
Jain Philip - Bangalore, IN
Sunil Kumar - Bangalore, IN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/08

US Classification:

370235

Abstract:

A method that includes determining a pending data packet count for one or more data packets associated with data to be forwarded from a node to another node on a communication link and then comparing the pending data packet count to a threshold data packet count value. The method further includes forwarding the one or more data packets to the other node at a rate based on the comparison.

US Patent:

7590135, Sep 15, 2009

Filed:

Dec 30, 2002

Appl. No.:

10/334894

Inventors:

Harlan T. Beverly - McDade TX, US
Quang Le - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12/56
H04J 1/16

US Classification:

370419, 370386, 370463

Abstract:

Methods and apparatus to perform security related operations on received signals are described. In one embodiment, a security device may perform security related operations on received signals and a logic (such as an Ethernet controller) may include an interface to provide communication with the security device. Other embodiments are also disclosed.

US Patent:

20060004983, Jan 5, 2006

Filed:

Jun 30, 2004

Appl. No.:

10/882986

Inventors:

Gary Tsao - Austin TX, US
Quang Le - Austin TX, US
Ashish Choubal - Austin TX, US
Hemal Shah - Austin TX, US

International Classification:

G06F 12/08

US Classification:

711202000, 711118000

Abstract:

Provided are a method, system, and program for managing memory options for a device such as an I/O device. Private addresses provided by logic blocks within the device may be transparently routed to either an optional external memory or to system memory, depending upon which of the optional memories the private address has been mapped.

US Patent:

20130271354, Oct 17, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/993115

Inventors:

Ramakanth Kondagunturi - Austin TX, US
Quang T. Le - Austin TX, US
Percy W. Wong - Austin TX, US

International Classification:

H04L 29/10

US Classification:

345 12

Abstract:

An embodiment of the invention includes a hardware architecture for, as an example, mobile computing devices. The architecture includes a physical layer that can be configured to be shared across one or more display panels that, in some instances, have different resolutions and bandwidth requirements. Using a shared physical layer removes one of the physical layers typically needed for multiple display devices (e.g., smart phones with two displays). In one embodiment, one physical layer includes two or more reference clock lanes so data lanes can be shared across two or more links The shared physical layer may be configured via a display driver. Other embodiments are described herein.

US Patent:

20180096667, Apr 5, 2018

Filed:

Sep 30, 2016

Appl. No.:

15/282777

Inventors:

- Santa Clara CA, US
Quang T. Le - Austin TX, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

G09G 5/00
H04N 19/91
G06T 1/60

Abstract:

In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The microcontroller can also store a number of received bits for each image component in a data structure and generate a pre-allocation signal indicating that additional bits of data for one of the image components are to be requested and stored in the data structure, wherein the pre-allocation signal is to be generated in response to determining that the counter is below the predetermined value. The microcontroller can also increase the counter by the predetermined value and transmit an address from the data structure to a display device in response to detecting a valid signal.

US Patent:

20160267883, Sep 15, 2016

Filed:

Mar 11, 2015

Appl. No.:

14/644767

Inventors:

- Santa Clara CA, US
Rajesh Poornachandran - Portland OR, US
Ajaya V. Durg - Austin TX, US
Arpit Shah - Austin TX, US
Anil K. Sabbavarapu - Austin TX, US
Nabil F. Kerkiz - Austin TX, US
Quang T. Le - Austin TX, US
Ryan R. Pinto - Austin TX, US
Moorthy Rajesh - Folsom CA, US
James A. Bish - Antelope CA, US
Ranjani Sridharan - Sunnyvale CA, US

International Classification:

G09G 5/36
G09G 5/395
G09G 5/00
G09G 5/393

Abstract:

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.