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Rajanish Donthi

age ~41

from Folsom, CA

Also known as:
  • H Donthi
Phone and address:
200 Moon Cir UNIT 228, Folsom, CA 95630
(818)6264353

Rajanish Donthi Phones & Addresses

  • 200 Moon Cir UNIT 228, Folsom, CA 95630 • (818)6264353
  • Rancho Cordova, CA
  • Northridge, CA
  • Sacramento, CA
  • Costa Mesa, CA

Resumes

Rajanish Donthi Photo 1

Rajanish Donthi

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Rajanish Donthi Photo 2

Rajanish "Raj" Donthi ([email protected])

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Position:
Validation Contractor at Intel
Location:
Sacramento, California Area
Industry:
Semiconductors
Work:
Intel since Jul 2009
Validation Contractor

Innovative Integration Sep 2008 - Feb 2009
Signal Processing Engineer

California State University, Northridge Jan 2008 - Aug 2008
Graduate Assistant

National Aerospace Laboratory Jan 2005 - Jul 2005
Engineering Intern
Education:
California State University-Northridge 2007 - 2008
M.S., Electrical EngineeringSome of Major Projects in area of ASIC, FPGA, Embedded system are given below Design of 16-bit Barrel Shifter *Full-custom physical layout design driven by a schematic-based design for 180nm ASIC *Verified design using DRC and LVS Flash based Wav music player *Designed Functionality and Implemented PSoC system in Quartus with memories and IO subsytem on cyclone II FPGA *Coded and debugged software using C in NIOS IDE Round-Robin controller and 32 bit barrel shifter *Implemented on Xilinx FPGA, RTL coded with VHDL, Synthesized, Simulated with ModelSim and Verified functionality Moving Ball on VGA Display using FPGA •Designed complex synchronous counters to develop a VGA timing generator for VGA interface and RGB data signals using VHDL and written C program to animate the ball Barcode Reader *Interfaced photo sensitive reader with microcontroller using SCI and software written in C language and also verified with PC using HyperTerminal via RS232 port
New Jersey Institute of Technology 2006 - 2006
M.S, Electrical Engineering
Synopsys IC Compiler Workshop
Visvesvaraya Technological University
Skills:
EDA/CAD Tools
Synopsys: IC Compiler
Design Compiler
Hspice
Mentor Graphics: IC Station
Design Architect
Modelsim
Xilinx: ISE
Coregen
Chipscope
Altera: Quartus
SOPC Builder
Cadence: NC-Verilog
SOC Encounter
Pspice
HDL: VHDL
Verilog
Development tool: NIOS IDE
ICC12 IDE
Assembly Language: 8085/8086
8051
Programming Language: Embedded C
MATLAB
C++
PERL (familiar)
OS environment: Macintosh OS X
UNIX (Solaris)
Windows XP/Vista
UML Modeling: Visio

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Rajanish Donthi Photo 3

Rajanish Donthi


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