Rajesh A Nair

US Patent:

6754216, Jun 22, 2004

Filed:

May 8, 2000

Appl. No.:

09/566602

Inventors:

Michael Wong - Fremont CA
Rajesh Nair - San Jose CA
Milan Momirov - San Francisco CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04L 1228

US Classification:

37039542, 3703957

Abstract:

A system enables a cell of data to be transmitted one time over a high speed data bus to an Ethernet switch system where it is then distributed to each of the destinations for which it is intended. A first group of buffers is for temporarily storing data that is to be delivered to only one destination. A second group of buffers is for holding the cells that are to be transmitted to a plurality of devices. In the described embodiment of the invention, the unicast and multicast cells are transmitted over the same line or bus. The invention further includes a switch processor that is formed to detect congestion within the switch fabric and to transmit a congestion rating to each device coupled to transmit and receive data through the switch fabric.

US Patent:

6792003, Sep 14, 2004

Filed:

Aug 12, 1999

Appl. No.:

09/373135

Inventors:

Somasekhar Potluri - Sunnyvale CA
Rajesh Gopal Nair - San Jose CA
Van A. Hunter - San Jose CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04J 300

US Classification:

370476, 370503, 370535, 375365

Abstract:

A method for transporting and aligning data across a set of serial data streams. The method includes creating a predetermined number of data streams from a first data stream. The first data stream has a first predetermined bit width and each data stream of the predetermined number of data streams has a second predetermined bit width smaller than the first predetermined bit width. In addition, the method includes inserting an alignment pattern in each of the predetermined number of smaller data streams. The predetermined number of smaller data streams are combinable into a data stream having the first predetermined bit width based on the alignment pattern. The method also includes preparing the predetermined number of smaller data streams for transmission. An apparatus for performing the method is also disclosed.

US Patent:

6865155, Mar 8, 2005

Filed:

May 8, 2000

Appl. No.:

09/566604

Inventors:

Michael Wong - Fremont CA, US
Rajesh Nair - San Jose CA, US
Milan Momirov - San Francisco CA, US

Assignee:

Nortel Networks Ltd. - St. Laurent

International Classification:

G08C015/00

US Classification:

370235, 370418

Abstract:

A switching system includes a switch fabric that includes groups of buffers for each port interface device that communicates with external communication devices through an Ethernet plane. The port interface device is formed to receive congestion ratings reflecting buffer usage within the switch fabric for each device coupled to transmit and receive packets through the switching fabric and to determine whether to route to the switching fabric or drop the packet based upon the congestion rating of the destination device and upon a quality of service rating for the packet.

US Patent:

6963563, Nov 8, 2005

Filed:

May 8, 2000

Appl. No.:

09/566603

Inventors:

Michael Wong - Fremont CA, US
Rajesh Nair - San Jose CA, US
Milan Momirov - San Francisco CA, US

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04L012/28

US Classification:

370389, 3703957, 370428, 370412, 370446

Abstract:

The present apparatus and method of use comprises a system that enables a cell of data to be transmitted one time over a high speed data bus to an switch system where it is then distributed to each of the destinations for which it is intended. A fabric access device and a multiplex devices are each formed to have groups of buffers for buffering signals according to type. The first group of buffers is for temporarily storing data that is to be delivered to only one destination. The second group of buffers is for holding the cells that are to be transmitted to a plurality of devices. In those embodiments in which the unicast and multicast cells are transmitted over the same line or bus a parsing unit examines a field within the header portion of each cell to determine whether the cell is a unicast or multicast cell. If the cell is a unicast cell, it is temporarily stored within the unicast receive buffer set. If the cell is a multicast cell, then it is temporarily stored in the multicast buffer set.

US Patent:

8069023, Nov 29, 2011

Filed:

Sep 2, 2008

Appl. No.:

12/202742

Inventors:

Jean-Marc Frailong - Los Altos CA, US
Jeffrey G. Libby - Cupertino CA, US
Jianhui Huang - Fremont CA, US
Sharada Yeluri - San Jose CA, US
Rajesh Nair - Fremont CA, US
John Keen - Mountain View CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

703 13, 370389, 370392

Abstract:

A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to extract read and write addressing from the nexthop instruction instead of performing this operation in microcode. A method for emulating a nexthop instruction in microcode with the assistance of dedicated hardware to compare a nexthop read address to a special value and to indicate whether the nexthop read address matches the special value, instead of performing this operation in microcode. A method for determining a network address by performing a single extraction of bit fields of a tree instruction to allow multiple tree search processes to be performed.

US Patent:

8520675, Aug 27, 2013

Filed:

Dec 23, 2008

Appl. No.:

12/343276

Inventors:

Jean-Marc Frailong - Los Altos CA, US
Jeffrey G. Libby - Cupertino CA, US
Anurag P. Gupta - Saratoga CA, US
John Keen - Mountain View CA, US
Rajesh Nair - Fremont CA, US
Avanindra Godbole - San Jose CA, US
Sharada Yeluri - San Jose CA, US

Assignee:

Juniper Networks, Inc. - Sunnyvale CA

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370390, 3702301, 370266, 370270, 370239, 370391, 370392, 370401, 370432

Abstract:

Methods and systems consistent with the present invention provide efficient packet replication in a router in order to multicast a stream of data. Packets are replicated and processed in a multithreaded environment. Embodiments consistent with the present invention implement a two-stage process for packet replication. The first stage thread will recirculate the packet to multiple second-stage threads. These second-stage threads will then create one or more outgoing copies of the packet. In this way, the copies are handled by multiple threads running in parallel.

US Patent:

20050281281, Dec 22, 2005

Filed:

Jul 13, 2005

Appl. No.:

11/181149

Inventors:

Rajesh Nair - Fremont CA, US
Komal Rathi - Sunnyvale CA, US
Somsubhra Sikdar - San Jose CA, US
Kevin Rowett - Cupertino CA, US

International Classification:

H04L012/28
H04L012/56

US Classification:

370419000

Abstract:

A system and device are disclosed for operating an interface circuit. The interface circuit comprises a buffer for buffering data, a parser interface for sending at least a portion of the buffered data to a direct execution parser, and a processing interface for sending at least a portion of the buffered data to a semantic processing unit. The system comprises a plurality of input buffers for buffering received data, a direct execution parser configured to parse the data in the input buffers in response to symbols in a parser stack, and a plurality of semantic processing units each configured to perform operations on data in the different input buffers according to commands from the direct execution parser.

US Patent:

20070019661, Jan 25, 2007

Filed:

Jul 20, 2005

Appl. No.:

11/186144

Inventors:

Kevin Rowett - Cupertino CA, US
Rajesh Nair - Fremont CA, US
Caveh Jalali - Redwood City CA, US
Joel Lach - Fremont CA, US

Assignee:

Mistletoe Technologies, Inc. - Cupertino CA

International Classification:

H04L 12/56

US Classification:

370419000

Abstract:

An embodiment of the invention is a processor comprising a direct execution parser configured to control the processing of digital data by semantically parsing data; a plurality of semantic processing units configured to perform data operations when prompted by the direct execution parser; and a plurality of output buffers for buffering data received from the plurality of semantic processing units. Another embodiment of the invention is an interface circuit comprising a packer circuit for receiving data from a semantic processing unit and a plurality of buffers for receiving the data. The interface circuit unloads the data received to an interface.