Rajesh Sankaran from Beaverton, OR, age 45

Resumes

Intel Fellow

view source

Location:

Hillsboro, OR

Industry:

Semiconductors

Work:

Intel Corporation
Intel Fellow
Intel Corporation
Senior Principal Engineer

Education:

Portland State University 1993 - 1995
Master of Science, Masters, Computer Engineering

Skills:

Virtualization
Operating Systems
Platform Architecture
Infiniband
Microprocessors
Computer Architecture
Network Virtualization
X86 Virtualization
I/O Virtualization
Debugging
System Architecture
Software Engineering
Device Drivers
Processors
Cpu Architecture
Accelerators

Rajesh Sankaran

view source

Rajesh Sankaran

view source

Us Patents

Synchronizing A Translation Lookaside Buffer With An Extended Paging Table
view source
US Patent:

8296546, Oct 23, 2012
Filed:

Jan 11, 2012
Appl. No.:

13/348608
Inventors:

Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Richard Uhlig - Hillsboro OR, US
Dion Rodgers - Hillsboro OR, US
Rajesh M Sankaran - Portland OR, US
Camron Rust - Hillsboro OR, US
Sebastian Schoenberg - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/10
US Classification:

711206, 711203, 711207, 711208, 711209
Abstract:

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Synchronizing A Translation Lookaside Buffer With An Extended Paging Table
view source
US Patent:

8601233, Dec 3, 2013
Filed:

Oct 23, 2012
Appl. No.:

13/658752
Inventors:

Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Richard A. Uhlig - Hillsboro OR, US
Scott Dion Rodgers - Hillsboro OR, US
Rajesh M. Sankaran - Portland OR, US
Camron B. Rust - Hillsboro OR, US
Sebastian Schoenberg - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G11C 15/00
US Classification:

711206, 711203, 711207, 711208, 711209
Abstract:

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Dynamic Mapping Of Guest Addresses By A Virtual Machine Monitor
view source
US Patent:

20080005447, Jan 3, 2008
Filed:

Jun 30, 2006
Appl. No.:

11/479731
Inventors:

Sebastian Schoenberg - Hillsboro OR, US
Andrew Anderson - Hillsboro OR, US
Steven M. Bennett - Hillsboro OR, US
Rajesh Sankaran - Portland OR, US
International Classification:

G06F 21/00
US Classification:

711 6
Abstract:

In a virtualization system comprising a guest machine, a host machine, and a virtual machine monitor (VMM), the host machine further including a processor including hardware support for virtualization the hardware support for virtualization at least in part to control operation of the guest machine, the VMM dynamically installing a mapping for a guest address to be accessed by the VMM in a page table of the VMM, prior to the VMM accessing the guest physical address.

Techniques And Mechanisms For Live Migration Of Pages Pinned For Dma
view source
US Patent:

20120254582, Oct 4, 2012
Filed:

Mar 31, 2011
Appl. No.:

13/076731
Inventors:

ASHOK RAJ - Portland OR, US
RAJESH M. SANKARAN - Portland OR, US
International Classification:

G06F 12/10
US Classification:

711206, 711E12061
Abstract:

Techniques for migrating data from a first range of physical memory locations to a second range of physical memory locations. The second range of physical memory locations is allocated for migration of data from the first range of physical memory locations Pending transactions for the first range of physical memory locations are flushed. One or more address translation entries are reprogrammed. Data is migrated from the first range of physical memory locations to the second range of physical memory locations. Subsequent memory transactions are processed to cause the transactions to be directed to the second range of physical memory locations.

Method And Apparatus For Tlb Shoot-Down In A Heterogeneous Computing System Supporting Shared Virtual Memory
view source
US Patent:

20130031333, Jan 31, 2013
Filed:

Jul 26, 2011
Appl. No.:

13/191327
Inventors:

Rajesh M. Sankaran - Portland OR, US
Altug Koker - Ed Dorado Hills CA, US
Philip R. Lantz - Cornelius OR, US
Asit K. Mallick - Saratoga CA, US
James B. Crossland - Banks OR, US
Aditya Navale - Folsom CA, US
Gilbert Neiger - Portland OR, US
Andrew V. Anderson - Forest Grove OR, US
International Classification:

G06F 12/10
US Classification:

711207, 711E12061
Abstract:

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Virtualizing Interrupt Priority And Delivery
view source
US Patent:

20130159579, Jun 20, 2013
Filed:

Dec 14, 2011
Appl. No.:

13/325714
Inventors:

Gilbert Neiger - Portland OR, US
Rajesh M. Sankaran - Portland OR, US
Gideon Gerzon - Ziehron Ya'akov, IL
Richard A. Uhlig - Hillsboro OR, US
Sergiu D. Ghetie - Hillsboro OR, US
Michael Neve de Mevergnies - Beaverton OR, US
Adil Karrar - San Francisco CA, US
International Classification:

G06F 13/26
US Classification:

710265
Abstract:

Embodiments of processors, methods, and systems for virtualizing interrupt prioritization and delivery are disclosed. In one embodiment, a processor includes instruction hardware and execution hardware. The instruction hardware is to receive a plurality of instructions, including a first instruction to transfer the processor from a root mode to a non-root mode for executing guest software in a virtual machine, wherein the processor is to return to the root mode upon the detection of any of a plurality of virtual machine exit events. The execution hardware is to execute the first instruction, execution of the first instruction to include determining a first virtual processor-priority value and storing the first virtual processor-priority value in a virtual copy of a processor-priority field, where the virtual copy of the processor-priority field is a virtual resource corresponding to a physical resource associated with an interrupt controller.

Synchronizing A Translation Lookaside Buffer With An Extended Paging Table
view source
US Patent:

20140059320, Feb 27, 2014
Filed:

Nov 3, 2013
Appl. No.:

14/070561
Inventors:

Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US
Gilbert Neiger - PORTLAND OR, US
Richard Uhlig - HILLSBORO OR, US
Dion Rodgers - Hillsboro OR, US
Rajesh M. Sankaran - Portland OR, US
Camron Rust - Hillsboro OR, US
Sebastian Schoenberg - HILLSBORO OR, US
International Classification:

G06F 12/10
US Classification:

711206
Abstract:

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Synchronizing A Translation Lookaside Buffer To An Extended Paging Table
view source
US Patent:

7555628, Jun 30, 2009
Filed:

Aug 15, 2006
Appl. No.:

11/504964
Inventors:

Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Richard Uhlig - Hillsboro OR, US
Dion Rodgers - Hillsboro OR, US
Rajesh Madukkarumukumana Sankaran - Portland OR, US
Camron Rust - Hillsboro OR, US
Sebastian Schoenberg - Hillsboro OR, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

G06F 12/10
US Classification:

711206, 711203, 711207, 711208, 711209
Abstract:

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.