Rajiv Kumar

US Patent:

6493852, Dec 10, 2002

Filed:

May 8, 2000

Appl. No.:

09/566683

Inventors:

Prakash Narain - San Carlos CA
Rajiv Kumar - Santa Clara CA

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4, 716 6

Abstract:

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, a method is provided for explicitly associating state information with variables of a language description of a hardware design. Information regarding the intended flow of logical signals among the variables, which represent interconnects in the hardware design through with the logical signals pass, is received. Then, the intended flow of logical signals is modeled by associating state information with the variables in accordance with the intended flow of logical signals. Advantageously, in this manner, the integrity of the data flow can be verified by confirming checks that are expressed as a function of the states associated with the variables.

US Patent:

6651228, Nov 18, 2003

Filed:

May 8, 2000

Appl. No.:

09/566684

Inventors:

Prakash Narain - San Carlos CA
Rajiv Kumar - Santa Clara CA
John M. Beardslee - Menlo Park CA
Rajeev K. Ranjan - Santa Clara CA
Christopher R. Morrison - Sunnyvale CA

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4

Abstract:

A method and apparatus are provided that facilitate analysis of the intended flow of logical signals between key points in a design. According to one aspect of the present invention, hardware design defects can be detected using a novel Intent-Driven Verification process. First, a representation of a hardware design and information regarding the intended flow of logical signals among variables in the representation are received. Then, the existence of potential errors in the hardware design may be inferred based upon the information regarding the intended flow of logical signals by (1) translating the information regarding the intended flow of logical signals into a comprehensive set of checks that must hold true in order for the hardware design to operate in accordance with the intended flow of logical signals, and (2) determining if any of the checks can be violated during operation of circuitry represented by the hardware design.

US Patent:

6839884, Jan 4, 2005

Filed:

Jan 18, 2001

Appl. No.:

09/766189

Inventors:

Prakash Narain - San Carlos CA, US
Rajeev K. Ranjan - Santa Clara CA, US
Christopher Morrison - Sunnyvale CA, US
John M. Beardslee - Menlo Park CA, US
Rajiv Kumar - Santa Clara CA, US

Assignee:

Real Intent, Inc. - Santa Clara CA

International Classification:

G06F 1750
G06F 945

US Classification:

716 5, 716 4

Abstract:

A method and apparatus are described that facilitate validation of a hardware design having multiple hierarchical levels. In one embodiment, a representation of the hardware design is received, and the hardware design is validated by performing validation processing on a plurality of sub-problems. Each of the plurality of sub-problems covers a computationally feasible size of the hardware design at a corresponding hierarchical level. In another embodiment, validation of a hardware design includes making use of validation processing previously performed with respect to one or more modules included in the hardware design based on the hierarchical relationship between these modules and other modules included in the hardware design.

US Patent:

20040117746, Jun 17, 2004

Filed:

Nov 18, 2003

Appl. No.:

10/717386

Inventors:

Prakash Narain - San Carlos CA, US
Rajiv Kumar - Santa Clara CA, US
John Beardslee - Menlo Park CA, US
Rajeev Ranjan - Santa Clara CA, US
Christopher Morrison - Sunnyvale CA, US

International Classification:

G06F017/50
G06F009/45

US Classification:

716/004000, 716/005000

Abstract:

Method and apparatus are provided for facilitating analysis of the intended behavior of a hardware design. According to one embodiment of the present invention, a language-based representation of a hardware design is received. Multiple design verification checks are generated for use in connection with model checking by applying a set of one or more predetermined properties to the language-based representation of the hardware design. Then, the hardware design, as implemented according to the language-based representation, is verified against intended behavior, represented by the set of one or more predetermined properties, by determining whether one or more of the design verification checks are violated by the hardware design. Finally, results of the verification may be reported.

US Patent:

53752422, Dec 20, 1994

Filed:

Sep 29, 1993

Appl. No.:

8/128385

Inventors:

Rajiv Kumar - Santa Clara CA
Paul Chan - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 945

US Classification:

395700

Abstract:

An improved compilation and linkage system for use in operating a computer to generate a cross-module optimized executable code file from a plurality of source files and object files. The source files are compiled to intermediate code files using a compiler sub-system. In the preferred embodiment of the present invention, the intermediate code files consist of intermediate language instructions that can be optimized for execution on a predetermined computer and a global symbol table. The compiler sub-system can also be used to generate conventional object code files if desired. A linkage sub-system is then used to cross-module optimize the code in a plurality of intermediate code files and link the resultant object code with any other object code files to generate the executable code file for execution on the computer in question. To the programmer, the operation of the compiler and linkage sub-systems of the present invention is essentially indistinguishable from that of a conventional compiler and linkage sub-system that lacks cross-module optimization.

US Patent:

62198254, Apr 17, 2001

Filed:

Jan 10, 1995

Appl. No.:

8/370963

Inventors:

Carl D. Burch - Mountain View CA
Rajiv Kumar - Santa Clara CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 945

US Classification:

717 4

Abstract:

A method of operating a digital computer to provide instrumentation data for a shared library running in an environment in which programs are loaded and unloaded by a loader. The environment supports the operation of at least one program in addition to the shared library, the program utilizing at least one function provided by the shared library. The operating environment includes storage for a predetermined environment variable that may be read by any program running in the environment. The method includes the steps of causing the loader to examine the environment to determine if the predetermined environment variable has been set; and storing profile based optimization data stored in the shared library code in a location specified by the predetermined environmental variable if the predetermined environmental variable was present in response to a command being sent to the loader. The profile based optimization data is normally stored when the shared library is unloaded from the operating environment by the loader.

US Patent:

20160025744, Jan 28, 2016

Filed:

Mar 13, 2014

Appl. No.:

14/774658

Inventors:

- Palo Alto CA, US
Hongjie DAI - Cupertino CA, US
Rajiv B. KUMAR - Palo Alto CA, US
Bo ZHANG - Stanford CA, US

International Classification:

G01N 33/68

Abstract:

Disclosed are methods and materials providing fluorescence detection of autoantibodies present in individuals who have developed or are at risk for type 1 diabetes. Provided is a plasmonic chip capable of fluorescence-enhancement of >100-fold. The fluorescent signal is generated by an anti-human antibody antibody, such as an anti-IgG antibody that is coupled to a fluorophore selected to emit at a wavelength enhanced by the plasmonic chip, for example in the NIR.