Rakesh A Patel

US Patent:

7132847, Nov 7, 2006

Filed:

Feb 24, 2004

Appl. No.:

10/708303

Inventors:

Wilson Wong - San Francisco CA, US
Rakesh Patel - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19/003

US Classification:

326 29, 326 86, 327170

Abstract:

A programmable technique is used to control the slew rate of a differential output buffer. A method controls the slew rate (SR) by changing an “on” resistance of the switches used to steer the current. This can be accomplished by (i) using different size switches or (ii) changing the slew rate of the predrivers which drive the final switches. The latter approach has the advantage that it only temporarily increases the “on” resistance, which does not cause any headroom problems after the transient. A specific application is for the differential outputs of a programmable logic integrated circuits.

US Patent:

7304494, Dec 4, 2007

Filed:

Apr 4, 2005

Appl. No.:

11/098832

Inventors:

Wilson Wong - San Francisco CA, US
Tim T Hoang - San Jose CA, US
Rakesh H Patel - Cupertino CA, US
Simardeep Maangat - Sunnyvale CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 17/16

US Classification:

326 26, 326 82

Abstract:

Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

US Patent:

7355462, Apr 8, 2008

Filed:

Jul 10, 2006

Appl. No.:

11/456484

Inventors:

Wilson Wong - San Francisco CA, US
Rakesh H. Patel - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 7/06

US Classification:

327156, 331 34

Abstract:

A digital controller for a voltage controlled oscillator (VCO) is provided within a phase lock loop (PLL). The digital controller includes a digital filter having first and second inputs for receiving upward and downward adjustment signals, respectively. The digital filter generates an increment signal and a decrement signal in response to the upward and downward adjustment signals, respectively. The digital controller includes a digital counter having first and second inputs for receiving the increment and decrement signals, respectively. The digital counter generates a multi-bit output signal that represents a running sum of the increment and decrement signals. The digital controller further includes a digital-to-analog converter (DAC) having an input for receiving the running sum output signal generated by the digital counter. The DAC is defined to generate a control voltage for the VCO in response to receipt of the running sum output signal from the digital counter.

US Patent:

7492816, Feb 17, 2009

Filed:

May 25, 2004

Appl. No.:

10/853987

Inventors:

Wilson Wong - San Francisco CA, US
Rakesh Patel - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 7/30

US Classification:

375232, 375228, 375345, 375219, 375220, 333 28 R, 702 69

Abstract:

A system includes a programmable transmitter device (e. g. , a PLD) connected to a programmable receiver device (e. g. , another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operation a low-speed communication link between the transmitter and receiver allows those devices to work together to transmit test signals having known characteristics from the transmitter to the receiver via the transmission medium, to analyze the test signals as received by the receiver, and to adjust at least some aspect of the system (e. g. , equalizer circuitry in the receiver) to at least partly compensate for losses in the test signals as received by the receiver.

US Patent:

7541857, Jun 2, 2009

Filed:

Dec 29, 2005

Appl. No.:

11/323571

Inventors:

Wilson Wong - San Francisco CA, US
Tin H. Lai - San Jose CA, US
Rakesh H. Patel - Cupertino CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03L 5/00

US Classification:

327317, 327 30

Abstract:

An impedance compensation circuit for inputs of a programmable device includes programmable impedance circuits connected with input nodes. The programmable impedance circuits can be configured to apply a compensating voltages to input nodes to reduce or eliminate unwanted offset voltages. An impedance compensation circuit may include resistors in series or current sources in parallel. A set of bypass switches selectively apply each resistor or current source to an input node, thereby changing the offset voltage of the node and compensating for impedance mismatches. Control logic provides signals to control the bypass switches. The control logic may be implemented using programmable device resources, enabling the control logic to be updated and improved after the manufacturing of the device is complete. The control logic can automatically evaluate offset voltages at any time and change compensating impedances accordingly. This reduces manufacturing costs and takes into account temperature and aging effects.

US Patent:

7590174, Sep 15, 2009

Filed:

Dec 20, 2005

Appl. No.:

11/312181

Inventors:

Wilson Wong - San Francisco CA, US
Rakesh H Patel - Cupertino CA, US
Tin H Lai - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03H 7/30
H03H 7/40
H03K 5/159

US Classification:

375229, 375230, 375231, 375232, 375233

Abstract:

Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

US Patent:

7616657, Nov 10, 2009

Filed:

Apr 11, 2006

Appl. No.:

11/402417

Inventors:

Bill W Bereza - Nepean, CA
Chong H Lee - San Ramon CA, US
Rakesh H Patel - Cupertino CA, US
Wilson Wong - San Francisco CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H04J 3/00

US Classification:

370464, 370518, 370536, 370465, 370468, 370503, 370373, 370376

Abstract:

High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

US Patent:

7646217, Jan 12, 2010

Filed:

Oct 5, 2006

Appl. No.:

11/539006

Inventors:

Ramanand Venkata - San Francisco CA, US
Rakesh H. Patel - Cupertino CA, US
Chong H. Lee - San Ramon CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

H01L 25/00

US Classification:

326 41, 326 37, 326 38, 326 47

Abstract:

In a programmable logic device, some or all of the parallel interconnect resources are replaced by serial interconnect resources within the device. Some or all of the functional blocks on the device are supplemented with serial interfaces. Although this makes the functional blocks more complex, it allows a significant reduction in the area consumed by interconnect resources. This translates into a significant reduction in device power consumption. The serial interfaces may operate synchronously from a global device clock (such as a PLL). In some cases, serial interfaces that are provided in the input/output blocks for external signalling can be omitted because the serial interfaces in the functional blocks can take over the external serial interface function as well, although in those cases the serial interfaces in the functional blocks would have to be more complex because they would have to be able to operate asynchronously with external devices.