Rakesh K Sanam

age ~51

from Rancho Santa Fe, CA

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Also known as:

Rakesh Kum Sanam
Rakesh S Kumar
Rakesh Banam
Rakesha M Sanam
Sanam K Rakesh
Rakes H Kumar
Sanam Rakesha

Connected to:

Rakesh Sanam Phones & Addresses

Rancho Santa Fe, CA
San Diego, CA
Encinitas, CA
2506 Dartford Bnd, Cedar Park, TX 78613 • (512)3519612
Richardson, TX
Dallas, TX
Broomfield, CO
Tempe, AZ
Longmont, CO
Travis, TX
Colton, TX

Work

Company:

Qualcomm
Aug 2012
Position:

Director of engineering

Education

Degree:

Master of Science, Masters
School / High School:

Arizona State University
1997 to 1998
Specialities:

Electrical Engineering, Vlsi Design

Skills

Verilog • Soc • Rtl Design • Systemverilog • Perl • Debugging • System on A Chip • Vmm • Ethernet • Pcie • Modelsim • System Verilog • Vera • Rvm • Uvm • C++ Modeling • Coverage Analysis • Vcs • Primetime • Design Compiler • Gate Eco • Formal Verification • Spyglass • Silicon Debug • Altera Quartus • Xilinx Ise • C • Tcl • Shell Scripting • Lisp • Expect • Linux Server Administration • Unix • Ethernet/Ip • Ieee 802.3 • Sonet/Sdh • Ata • Processor/Peripheral Integration

Industries

Semiconductors

Us Patents

Synchronization Mechanism For Image Capture And Processing Systems
view source
US Patent:

20210337117, Oct 28, 2021
Filed:

Dec 1, 2020
Appl. No.:

17/109009
Inventors:

- San Diego CA, US
Scott CHENG - Foothill Ranch CA, US
Rohan DESAI - San Diego CA, US
Jiafu LUO - Irvine CA, US
Krishnam INDUKURI - San Diego CA, US
Abhay RAUT - San Diego CA, US
Rakesh SANAM - Rancho Santa Fe CA, US
Chia-Yuan TENG - San Diego CA, US
Chinchuan CHIU - Poway CA, US
International Classification:

H04N 5/232
Abstract:

Techniques and systems are provided for processing image data. For example, an image signal processor can obtain (e.g., from a host processor) a first setting change indicator value indicating a change in parameter settings of the image signal processor. The image signal processor can obtain an image frame from an image sensor, and can determine a second setting change indicator value from the image frame. The second setting change indicator value can be provided to the image sensor from the host processor. The second setting change indicator value indicates a change in parameter settings of the image sensor. The image signal processor can compare the first setting change indicator value to the second setting change indicator value, and can determine whether to process the image frame or to drop the image frame based on comparing the first setting change indicator value to the second setting change indicator value.

Resumes

Director Of Engineering

view source

Location:

San Diego, CA

Industry:

Semiconductors

Work:

Qualcomm
Director of Engineering
Cisco Jan 2006 - Jul 2012
Technical Leader, Asic Engineering
Cisco Aug 2000 - Dec 2005
Senior Asic Engineer
Lucent Microelectronics-Bell Labs 1999 - 2000
Member of Technical Staff- Asic Design
Texas Instruments 1998 - 1999
Design Engineer Intern

Education:

Arizona State University 1997 - 1998
Master of Science, Masters, Electrical Engineering, Vlsi Design Jawaharlal Nehru Technological University 1993 - 1997
Bachelors, Bachelor of Technology, Electronics, Engineering, Communications

Skills:

Verilog
Soc
Rtl Design
Systemverilog
Perl
Debugging
System on A Chip
Vmm
Ethernet
Pcie
Modelsim
System Verilog
Vera
Rvm
Uvm
C++ Modeling
Coverage Analysis
Vcs
Primetime
Design Compiler
Gate Eco
Formal Verification
Spyglass
Silicon Debug
Altera Quartus
Xilinx Ise
C
Tcl
Shell Scripting
Lisp
Expect
Linux Server Administration
Unix
Ethernet/Ip
Ieee 802.3
Sonet/Sdh
Ata
Processor/Peripheral Integration