Ramsey H Haddad

US Patent:

6363471, Mar 26, 2002

Filed:

Jan 3, 2000

Appl. No.:

09/476323

Inventors:

Stephan G. Meier - Sunnyvale CA
Bruce A. Gieseke - San Jose CA
William A. McGee - San Jose CA
Ramsey W. Haddad - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1200

US Classification:

711220, 708491

Abstract:

A processor includes an address generation unit (AGU) which adds address operands and the segment base. The AGU may add the segment base and the displacement while other address operands are being read from the register file. The sum of the segment base and the displacement may subsequently be added to the remaining address operands. The AGU receives the addressing mode of the instruction, and if the addressing mode is 16 bit, the AGU zeros the carry from the sixteenth bit to the seventeenth bit of the sums generated therein. Additionally, in parallel, the AGU determines if a carry from the sixteenth bit to the seventeenth bit would occur if the logical address were added to the segment base. In one embodiment, the sum of the address operands and the segment base, with carries from the sixteenth bit to the seventeenth bit zeroed, and the carry generated in parallel are provided to a translation lookaside buffer (TLB), which stores translations in the same format (sum and carry). In another embodiment, the AGU corrects the most significant bits of the generated sum based on the carry.

US Patent:

6481251, Nov 19, 2002

Filed:

Oct 25, 1999

Appl. No.:

09/433184

Inventors:

Stephan G. Meier - Sunnyvale CA
Ramsey W. Haddad - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 300

US Classification:

70 52, 710 39, 710112, 711100, 711141

Abstract:

A processor includes a store queue and a store queue number assignment circuit. The store queue number assignment circuit assigns store queue numbers to stores, and operates upon instruction operations prior to the instruction operations reaching a point in the pipeline of the processor at which out of order instruction processing begins. Thus, store queue entries may be reserved for stores according to the program order of the stores. Additionally, in one embodiment, the store queue number identifying the youngest store represented in the store queue may be assigned to loads. In this manner, loads may determine which stores in the store queue are older or younger than the load based on relative position within the store queue. Checking for store queue hits may be qualified with the entries between the head of the store queue and the entry indicated by the loads store queue number. In one particular embodiment, the store queue number may include an additional âtoggleâ bit which is toggled each time the assignment of store queue numbers reaches the maximum store queue entry and wraps to zero.

US Patent:

6542984, Apr 1, 2003

Filed:

Jan 3, 2000

Appl. No.:

09/476578

Inventors:

James B. Keller - Palo Alto CA
Ramsey W. Haddad - Cupertino CA
Stephan G. Meier - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1576

US Classification:

712214

Abstract:

A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be incorrectly executed, the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Furthermore, the scheduler may employ a more aggressive scheduling mechanism since the penalty for incorrect execution is reduced. Additionally, the scheduler maintains the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well.

US Patent:

6564315, May 13, 2003

Filed:

Jan 3, 2000

Appl. No.:

09/476322

Inventors:

James B. Keller - Palo Alto CA
Ramsey W. Haddad - Cupertino CA
Stephan G. Meier - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9312

US Classification:

712214, 712235

Abstract:

A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be required to execute non-speculatively, the particular instruction operation is still stored in the scheduler. Subsequent to determining that the particular operation has become non-speculative (through the issuance and execution of instruction operations prior to the particular instruction operation), the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations which are to execute non-speculatively may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Additionally, the scheduler may maintain the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications.

US Patent:

6622235, Sep 16, 2003

Filed:

Jan 3, 2000

Appl. No.:

09/476204

Inventors:

James B. Keller - Palo Alto CA
Ramsey W. Haddad - Cupertino CA
Stephan G. Meier - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 938

US Classification:

712 23, 712214, 712216

Abstract:

A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the memory operation after issuance. If a condition occurs which prevents correct execution of the memory operation, the memory operation is retried. The scheduler subsequently reschedules and reissues the memory operation in response to the retry. Additionally, the scheduler may receive a retry type indicating the reason for retry. Certain retry types may indicate a delayed reissuance of the memory operation until the occurrence of a subsequent event. In response to such retry types, the scheduler monitors for the subsequent event and delays reissuance until the event is detected. The scheduler may include a physical address buffer to detect a load memory operation which incorrectly issued prior to an older store memory operation upon which it is dependent for the memory operation. The scheduler may also include a store tag buffer to detect that a load memory operation is to be reissued due to the reissuance of a store memory operation on which the load was determined to be dependent during the previous execution of the load memory operation.

US Patent:

6622237, Sep 16, 2003

Filed:

Jan 3, 2000

Appl. No.:

09/476192

Inventors:

James B. Keller - Palo Alto CA
Thomas S. Green - Sunnyvale CA
Wei-Han Lien - Sunnyvale CA
Ramsey W. Haddad - Cupertino CA
Keith R. Schakel - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 900

US Classification:

712216, 712214, 712 23

Abstract:

A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e. g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores.

US Patent:

6651161, Nov 18, 2003

Filed:

Jan 3, 2000

Appl. No.:

09/476937

Inventors:

James B. Keller - Palo Alto CA
Thomas S. Green - Sunnyvale CA
Wei-Han Lien - Sunnyvale CA
Ramsey W. Haddad - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 900

US Classification:

712216, 712 23, 712225

Abstract:

A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e. g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores.

US Patent:

6694424, Feb 17, 2004

Filed:

Jan 3, 2000

Appl. No.:

09/476579

Inventors:

James B. Keller - Palo Alto CA
Thomas S. Green - Sunnyvale CA
Wei-Han Lien - Sunnyvale CA
Ramsey W. Haddad - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 900

US Classification:

712216, 712 23, 712225

Abstract:

A processor employs a store to load forward (STLF) predictor which may indicate, for dispatching loads, a dependency on a store. The dependency is indicated for a store which, during a previous execution, interfered with the execution of the load. Since a dependency is indicated on the store, the load is prevented from scheduling and/or executing prior to the store. The STLF predictor is trained with information for a particular load and store in response to executing the load and store and detecting the interference. Additionally, the STLF predictor may be untrained (e. g. information for a particular load and store may be deleted) if a load is indicated by the STLF predictor as dependent upon a particular store and the dependency does not actually occur. In one implementation, the STLF predictor records at least a portion of the PC of a store which interferes with the load in a first table indexed by the load PC. A second table maintains a corresponding portion of the store PCs of recently dispatched stores, along with tags identifying the recently dispatched stores.