Ramya Balasundaram from 11313 Cherisse Dr, Austin, TX 78739, age 45

Ramya Balasundaram Phones & Addresses

11313 Cherisse Dr, Austin, TX 78739
College Station, TX
947 30Th St, Los Angeles, CA 90007
2632 Ellendale Pl, Los Angeles, CA 90007 • (323)7343014
2618 Ellendale Pl, Los Angeles, CA 90007
1209 27Th St, Los Angeles, CA 90007
San Juan Capistrano, CA
Sunnyvale, CA

Work

Company:

Cirrus logic
Nov 2009
Position:

Analog and mixed signal ic design engineer

Education

School / High School:

Texas A&M University

Skills

Analog • Mixed Signal • Analog Circuit Design • Asic • Integrated Circuit Design • Circuit Design • Cmos • Verilog • Perl Script • Mixed Signal Ic Design • Ic • Perl • Cadence Virtuoso • Semiconductors • Debugging • Vlsi • Spice

Industries

Semiconductors

Us Patents

Random Telegraph Signal Identification And Measurement
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US Patent:

20160366656, Dec 15, 2016
Filed:

Jun 7, 2016
Appl. No.:

15/175871
Inventors:

- Edinburgh, GB
Aaron J. BRENNAN - Austin TX, US
Justin DOUGHERTY - Austin TX, US
Ramya BALASUNDARAM - Austin TX, US
Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh
International Classification:

H04W 52/36
H04W 52/32
Abstract:

In accordance with embodiments of the present disclosure, a method for identifying a location of an integrated circuit that is sensitive to RTS noise may include applying localized heat to a scan area of the integrated circuit, observing any change in one or more electrical parameters of the integrated circuit in response to the localized heat being applied to the scan area indicative of sensitivity to RTS noise, and identifying the location sensitive to RTS noise responsive to observing change in one or more electrical parameters of the integrated circuit indicative of sensitivity to RTS noise in response to the localized heat being applied to the scan area.

Resumes

Analog And Mixed Signal Ic Design Engineer

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Location:

11313 Cherisse Dr, Austin, TX 78739

Industry:

Semiconductors

Work:

Cirrus Logic
Analog and Mixed Signal Ic Design Engineer
Broadcom Jan 2009 - May 2009
Intern
Broadcom Corporation Pll Group Central Engineering May 2007 - Aug 2007
Intern

Education:

Texas A&M University
Birla Institute of Technology and Science, Pilani
University of Southern California

Skills:

Analog
Mixed Signal
Analog Circuit Design
Asic
Integrated Circuit Design
Circuit Design
Cmos
Verilog
Perl Script
Mixed Signal Ic Design
Ic
Perl
Cadence Virtuoso
Semiconductors
Debugging
Vlsi
Spice