Randall J Rorden

US Patent:

49949632, Feb 19, 1991

Filed:

Nov 1, 1988

Appl. No.:

7/266381

Inventors:

Randall J. Rorden - Orem UT
Ronald B. Arthur - Provo UT
Michael E. Rex - Orem UT
Darryl J. Stewart - Provo UT
Mark Muhlestein - Orem UT
Dennis A. Fairclough - Orem UT

Assignee:

Icon Systems International, Inc. - Orem UT

International Classification:

G06F 1516

US Classification:

364200

Abstract:

A system for providing a high speed digital communication path between the processor of a host computer and the processors of one or more remote computers. The high speed digital communication path allows a remote computer to efficiently share the resources of the larger host computer such as high speed magnetic disk drives and printers. A host interface located at the host computer is connected to the internal host bus of the host computer. The host interface includes a host port and components which provide for the transfer of data from the host bus to the host port. The data bits presented at the host port are arranged in a parallel format. A communication cable conveys the parallel data bits from the host port to a remote port in a remote interface at a remote computer. The remote interface provides a random access memory and components for transferring data from the remote bus to the random access memory and vice-versa. Data bits presented at the remote port are also conveyed to the random access memory.

US Patent:

48397962, Jun 13, 1989

Filed:

Jul 16, 1987

Appl. No.:

7/075063

Inventors:

Randall J. Rorden - Orem UT
Ronald B. Arthur - Provo UT
Mark Muhlestein - Orem UT

Assignee:

Icon International, Inc. - UT

International Classification:

G06F 1200

US Classification:

364200

Abstract:

A digital memory system wherein a plurality of frames in the memory, each frame holding a page of data, may be rapidly accessed utilizing static column dynamic random access memories (SCRAMs). The SCRAM devices are configured such that a page of data is located on corresponding rows of a plurality of SCRAM devices, the corresponding rows being referred to as frames. Once a row has been activated into static column mode, successive accesses to the same row may be made very rapidly. In the presently preferred embodiments, a plurality of banks are provided, each bank being capable of holding one page of data in static column mode. In the preferred embodiments, a tag register and comparator are provided which are associated with each bank. The tag register contains a portion of the address which previously caused an access to its corresponding bank. An address is presented to all the tag registers and comparators.

US Patent:

49145770, Apr 3, 1990

Filed:

Jul 16, 1987

Appl. No.:

7/074310

Inventors:

Darryl J. Stewart - Provo UT
Randall J. Rorden - Orem UT
Mark Muhlestein - Orem UT

Assignee:

ICON International, Inc. - Orem UT

International Classification:

G06F 1210

US Classification:

364200

Abstract:

A system and method for allowing dynamic configuration of the translation entries within a memory management system of a computer. In the disclosed embodiment, portions of a logical address from a CPU are defined as offset, page, volume/page, and volume fields. The offset field is presented unaltered to a main memory to select a specific location within a page of memory. The page field forms a first portion of the address of a selected entry in the translation memory. The volume/page field is combined with the contents of a base register as specified by the contents of a mask register to form the remaining portion of the address of a selected entry in the translation memory. The volume field and volume/page fields are compared to one or more tags stored in the translation memory to determine if a match exists. If a match exists, the frame pointer associated with the matching tag is output to main memory as the physical address of the frame containing the desired page.