Randy K Bailey

US Patent:

6570397, May 27, 2003

Filed:

Aug 7, 2001

Appl. No.:

09/923548

Inventors:

Romi Mayder - San Jose CA
Noriyuki Sugihara - Campbell CA
Andrew Tse - Castro Valley CA
Randy L. Bailey - Fort Collins CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G01R 3102

US Classification:

324754, 3241581

Abstract:

Systems and methods for calibrating the timing of electronic circuit testers and verifying the timing calibration of electronic circuit testers are described. In some embodiments, a calibration reference signal is transmitted from the test head directly through the load board interface, rather than through external instruments, so that timing errors associated with external wires and cables may be avoided. The timing calibration and timing calibration verification functionality is provided on a single calibration board, thereby reducing the calibration set-up time relative to conventional robot-based calibrators. In addition, a high pin count electronic circuit testers may be calibrated by a calibration board that is configured to calibrate one subset of the test channels at a time. In some embodiments, test channels are connected directly to calibration board comparators to avoid the accumulated signal degradation and the signal path route errors that may result from transmitting tester channel signals through a mechanical relay selection matrix.

US Patent:

7106081, Sep 12, 2006

Filed:

Jul 8, 2004

Appl. No.:

10/886848

Inventors:

Romi Mayder - San Jose CA, US
Todd Sholl - San Jose CA, US
Nasser Ali Jafari - Falls Church VA, US
Andrew Tse - Castro Valley CA, US
Randy L. Bailey - Fort Collins CO, US

Assignee:

Verigy IPco - Singapore

International Classification:

G01R 31/02

US Classification:

324758

Abstract:

A parallel calibration system for an electronic circuit tester comprises test and measurement electronics, a test fixture coupled to the test and measurement electronics, the test fixture comprising clock reference circuitry and clock distribution circuitry, a device under test interface, and a plurality of calibration boards coupled to the device under test interface, wherein the plurality of calibration boards and the clock distribution circuitry simultaneously test the signal paths of a plurality of test channels.