Randy I Oyadomari from San Jose, CA, age 52

Resumes

Senior Design Engineer

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Location:

San Jose, CA

Industry:

Semiconductors

Work:

Quicklogic
Senior Design Engineer
Jdsu 2009 - 2012
Senior Design Engineer
Finisar Corporation (Nasdaq: Fnsr) 2001 - 2009
Senior Design Engineer
Quicklogic 1998 - 2001
Design Engineer
Quicklogic 1994 - 1998
Applications Engineer

Skills:

Fpga
Hardware Architecture
Semiconductors
Embedded Systems
Verilog
Debugging
Electronics
Rtl Design
Vhdl
Hw Design
System Architecture
Fpga Design
Simulation

Us Patents

Multiple Domains In A Multi-Chassis System
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US Patent:

7630385, Dec 8, 2009
Filed:

Aug 4, 2006
Appl. No.:

11/462669
Inventors:

Randy I. Oyadomari - San Jose CA, US
George A. Bullis - Glendora CA, US
Minh Q. Vu - San Jose CA, US
International Classification:

H04Q 11/00
H04L 12/28
G06F 15/16
G06F 11/00
US Classification:

370400, 370218, 370252, 370386, 370466, 709220, 709238, 709250, 714 11, 714 27, 714 46, 714 57
Abstract:

Creation of port domains in a multi-chassis system. The multi-chassis system includes two or more chassis that each includes one or more blades. In one embodiment, a sync group of at least two chassis is created, typically by connecting the two or more chassis with an interconnection means such as a sync-cable. Then, two or more ports of the sync group are selected for inclusion in a port domain. The locations of the ports relative to each other is then determined. Finally, a port domain is generated based on the relative locations of the ports and port domain generation rules. If the ports are on separate chassis, then a global domain is generated if a predetermined number of global domains do not already exist and if the ports are on the same chassis, a local domain is generated regardless of the number of global domains.

Efficient Transmission Of Digital Return Path Data In Cable Television Return Path
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US Patent:

7725036, May 25, 2010
Filed:

Nov 8, 2002
Appl. No.:

10/291208
Inventors:

Gerald F. Sage - Chico CA, US
Randy Ichiro Oyadomari - San Jose CA, US
Assignee:

Finisar Corporation - Sunnyvale CA
International Classification:

H04B 10/12
US Classification:

398141, 398154, 398 77, 398 78, 398115
Abstract:

An efficient means for transmitting digitized return path signals over a cable television return path is disclosed. In one embodiment of the invention, the cable television return path includes a node that receives an analog return signal from a subtree of the cable television system and generates a digital transport signal representative of the analog return path signal. The digital transport signal, however, is not a digitized form of the analog return signal. Rather, the digital transport signal is encoded such that fewer bits are used to represent the analog return signal without substantially impacting the accuracy and dynamic range of the signal. At the hub, the digital transport signal is decoded and converted to produce an analog signal that is a close approximation of the analog return signal.

Arm And Rollback In A Multi-Chassis System
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US Patent:

7764695, Jul 27, 2010
Filed:

Sep 25, 2006
Appl. No.:

11/534916
Inventors:

Randy I. Oyadomari - San Jose CA, US
George A. Bullis - Glendora CA, US
Minh Q. Vu - San Jose CA, US
International Classification:

H04Q 11/00
H04L 12/56
US Classification:

370400, 370218, 370252, 370386, 370466, 709220, 709238, 709250, 714 11, 714 27, 714 46, 714 57
Abstract:

A multi-chassis system includes at least a first chassis and a second chassis that each includes one or more blades. The one or more blades in turn include one or more ports. The two or more chassis are connected through use of an interconnector. The multi-chassis system may also include access to one or more microprocessors that may execute thereon software that controls the propagation of the arm condition. The arm condition is generated at a first port of a first chassis or network analyzer blade coupled to the first chassis. The arm condition is then transmitted to one or more additional ports of the first chassis while not being transmitted to any ports of the second chassis. Finally, the reception of a precondition for triggering defined by the arm condition is limited to those ports that have received the arm condition.

Changing Communication Mode In A Catv Pathway Using Mute Commands
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US Patent:

7765576, Jul 27, 2010
Filed:

May 12, 2004
Appl. No.:

10/845006
Inventors:

Randy Ichiro Oyadomari - San Jose CA, US
Arthur Michael Lawson - Morgan Hill CA, US
Stephen Charles Gordy - Sunnyvale CA, US
Assignee:

Finsiar Corporation - Sunnyvale CA
International Classification:

H04N 7/173
US Classification:

725129, 398115
Abstract:

A cable node and a cable hub that communicate on a CATV network are configured to switch communication modes without signal loss or degradation due to delays in switching communication modes. In particular, a cable node sends one or more mute commands in an outgoing data stream to the cable hub, causing the cable hub to disable the RF outputs. Afterward, or along with the one or more mute commands, the cable node can send a switch mode command, thereby causing the cable hub to switch to the appropriate next communication mode, such as a communication mode using a new compression rate. When the cable hub has switched to the appropriate next communication mode, the cable hub can then properly receive and decode a corresponding data stream using the next communication mode.

Discovery And Self-Organization Of Topology In Multi-Chassis Systems
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US Patent:

7827248, Nov 2, 2010
Filed:

Jun 14, 2004
Appl. No.:

10/868631
Inventors:

Randy Oyadomari - San Jose CA, US
George Bullis - Glendora CA, US
Ken Hornyak - San Jose CA, US
Scott Baxter - Menlo Park CA, US
Stephen Strong - Fremont CA, US
Doug Durham - Sunnyvale CA, US
International Classification:

G06F 13/00
US Classification:

709208, 709214, 709224, 715736
Abstract:

Multi-chassis systems determine their topology and self-organize through a discovery process. The systems include one or more chassis, each with individual blades and ports, which are serially chained together. When the discovery process is initiated, chassis identification data in buffers in each chassis is propagated to adjacent chassis and is then used to initiate communication via a network connection. Once the chassis are able to communicate via the network connection, at least one chassis in the system receives the chassis identification data of each chassis and can thereby identify each chassis. The chain is then divided into one or more sync-groups and master and slave chassis are designated. Each sync-group is configured to ignore data from other sync-groups. Domains are also configured from sets of ports within each sync-group.

Single Master Clock Control Of Ethernet Data Transfer Over Both A Cable Tv Return Path And An Ethernet Forward Path
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US Patent:

8032916, Oct 4, 2011
Filed:

Aug 2, 2004
Appl. No.:

10/909478
Inventors:

Randy Ichiro Oyadomari - San Jose CA, US
Arthur Michael Lawson - Morgan Hill CA, US
Stephen Charles Gordy - Sunnyvale CA, US
Assignee:

Finisar Corporation - Sunnyvale CA
International Classification:

H04N 7/173
H04L 5/14
H04L 12/28
H04L 12/56
H04L 7/00
H04L 7/06
H04J 3/06
H04J 3/04
H04J 3/02
US Classification:

725119, 370294, 37039562, 370503, 370518, 370535, 370537, 375355, 375356, 375358, 375364
Abstract:

An optical signal return path system analog RF signals are sampled using a master clock frequency, and combined with digital data such as Ethernet data at a cable node. The cable node sends the combined signals on a return path over a fiber optic medium to the cable hub. The cable hub extracts an approximate in-frequency replicate of a master clock signal, and can use the replicate master clock signal to desample the digitized RF signals back to analog. The cable hub can further use the replicate of the master clock signal to serialize Ethernet data, and send the Ethernet data back to the cable node via an optical cable in the forward direction. Accordingly, a single master clock signal can be used on a CATV network for encoding/decoding, and transmitting a variety of data signals, which enhances the integrity and reliability of the data signals.

Synchronization Of Timestamps To Compensate For Communication Latency Between Devices
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US Patent:

8190722, May 29, 2012
Filed:

Jun 30, 2004
Appl. No.:

10/882711
Inventors:

Randy Oyadomari - San Jose CA, US
Arthur Michael Lawson - Morgan Hill CA, US
International Classification:

G06F 15/16
US Classification:

709223, 709248, 709250, 370301, 702 89, 710118, 713375, 713400, 713401
Abstract:

Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment, it can be determined how long it takes to propagate a signal to each box in the chain. These values are then recorded in each box in a delay register so that each box has a recorded delay value corresponding to the time required to propagate a signal to or receive a signal from every other box. Each box applies a control signal, such as a run signal or a trigger signal, to the ports in the box only after the expiration of the delay value indicated in the delay register. The box initiating the signal has the largest delay since the other boxes need to get the signal before the boxes can begin to operate with a common counter, with successive boxes having smaller delays.

Propagation Of Signals Between Devices For Triggering Capture Of Network Data
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US Patent:

8266271, Sep 11, 2012
Filed:

Jun 30, 2004
Appl. No.:

10/881620
Inventors:

Randy Oyadomari - San Jose CA, US
Stephen Strong - Fremont CA, US
Assignee:

JDS Uniphase Corporation - Milpitas CA
International Classification:

G06F 15/173
US Classification:

709224, 709223, 709228, 709248
Abstract:

Protocol analyzers systems and methods coordinate the capture of network data of interest across multiple chassis. Each chassis has individual blades with accompanying ports and is serially connected to other chassis in the system. Selected ports from each chassis are configured in domains that can be spread across the serially connected chassis and used in coordination to capture network data of interest. A serial protocol containing control signals is used to transmit run, stop, and trigger data between the serially connected chassis and thereby coordinate the activity of ports within each domain. Through the use of the serial protocol the number of wires connecting adjacent chassis is minimized and each of the blades in the multi-chassis systems can be synchronously started, stopped, and triggered at the same time to synchronously capture the network data of interest.