Randy L Roberson

US Patent:

7330955, Feb 12, 2008

Filed:

Oct 18, 2004

Appl. No.:

10/967615

Inventors:

Randy L. Roberson - New Port Richey FL, US
Tarun Thakur - Colorado Springs CO, US
Clark Edward Lubbers - Colorado Springs CO, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 12/00

US Classification:

711170

Abstract:

A data storage system is provided comprising memory allocation information associated with a change in a system configuration of memory allocation within a memory space, and means for updating the system configuration by saving the memory allocation information before updating the system configuration. A recovery record comprises memory allocation information associated with the change in system configuration of memory allocation, and a completion indicator comprises a first value if the memory allocation information is included in the system configuration and comprises a second value if the memory allocation information is not included in the system configuration.

US Patent:

7441106, Oct 21, 2008

Filed:

Jul 2, 2004

Appl. No.:

10/884602

Inventors:

Randy L. Roberson - New Port Richey FL, US
Tarun Thakur - Fremont CA, US
Justus Joseph Pendleton - Colorado Springs CO, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 9/302

US Classification:

712221, 712 28

Abstract:

Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet comprising a corresponding simplex operation and remainder. The packet is communicated to a second processing unit which processes the packet to arrive at a result for the complex operation, preferably by arriving at a result for the simplex operation and combining this result with the remainder. In this way, inter-processor operations can be efficiently encoded and distributed to meet the requirements of a given architecture. Preferably, the first processing unit determines the remainder by separately arriving at the result for the complex operation. The complex operation is preferably characterized as a mathematical operation on a non-power of two operand (e. g. , 30), and the simplex operation is characterized as a mathematical operation on a power of two operand (e. g. , 32).

US Patent:

7594075, Sep 22, 2009

Filed:

Oct 20, 2004

Appl. No.:

10/969580

Inventors:

Randy L. Roberson - New Port Richey FL, US
Clark Edward Lubbers - Colorado Springs CO, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 12/16

US Classification:

711114, 711202

Abstract:

Metadata architecture and associated methodology for a data storage system employing a grid-based storage capacity wherein each grid defines a storage unit in terms of a plurality of storage domains along one axis against one or more rows of a plurality of storage stripes along another axis, and wherein a grid grouping of two or more grids defines a sheet of data storage capacity. The metadata comprises identification information stored in a memory space characterizing an allocation status of the sheets in the storage capacity. A method is provided for allocating memory for the grid-based storage capacity comprising determining whether the allocation is associated with an existing logical device. If the determining step is associated with an existing logical device, then a logical device allocation map and a sheet allocation table are accessed to allocate a selected storage unit. Otherwise, a sheet allocation descriptor and a sheet allocation map are accessed to allocate a selected storage unit.

US Patent:

7882271, Feb 1, 2011

Filed:

Jul 30, 2007

Appl. No.:

11/830201

Inventors:

Clark Edward Lubbers - Colorado Springs CO, US
Robert George Bean - Colorado Springs CO, US
Randy L. Roberson - Spring Hill FL, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 3/00
G06F 13/00

US Classification:

710 5, 710 33, 711118, 707694

Abstract:

An apparatus and associated method are provided for performing a storage transaction associated with a network I/O command by employing an ASIC having an interconnect selectively coupling a plurality of dedicated purpose function controllers in the ASIC to a policy processor via a list manager in the ASIC communicating on a peripheral device bus to which the policy processor is connected.

US Patent:

8086820, Dec 27, 2011

Filed:

Jun 29, 2007

Appl. No.:

11/771881

Inventors:

Clark Edward Lubbers - Colorado Springs CO, US
Randy L. Roberson - Spring Hill FL, US

Assignee:

Seagate Technology LLC - Cupertino CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 9/26
G06F 9/34

US Classification:

711200, 711118, 711131

Abstract:

Apparatus and method for highly efficient data queries. In accordance with various embodiments, a data structure is provided in a memory space with a first portion characterized as a virtual data space storing non-sequential entries and a second portion characterized as a first data array of sequential entries. At least a first sequential entry of the data array points to a skip list, at least a second sequential entry of the data array points to a second data array, and at least a third sequential entry points to a selected non-sequential entry in the first portion.

US Patent:

8131969, Mar 6, 2012

Filed:

Oct 20, 2004

Appl. No.:

10/969648

Inventors:

Randy L. Roberson - New Port Richey FL, US
Clark Edward Lubbers - Colorado Springs CO, US
Tarun Thakur - Fremont CA, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 13/00

US Classification:

711170, 711155, 711167

Abstract:

A data storage system and associated method comprising system configuration information; a first processor adapted for identifying a portion of the system configuration information in response to a configuration change request to the memory space, and for signaling an update request incident with the configuration change request to a second processor; and a second processor adapted for updating the portion in response to the update request and independently of the first processor.

US Patent:

20090006804, Jan 1, 2009

Filed:

Jun 29, 2007

Appl. No.:

11/771685

Inventors:

CLARK EDWARD LUBBERS - COLORADO SPRINGS CO, US
RANDY L. ROBERSON - SPRING HILL FL, US

Assignee:

Seagate Technology LLC - Scotts Valley CA

International Classification:

G06F 12/02

US Classification:

711203, 711E12002

Abstract:

Apparatus and method for accessing a virtual storage space. The space is arranged across a plurality of storage elements, and a skip list is used to map as individual nodes each of a plurality of non-overlapping ranges of virtual block addresses of the virtual storage space from a selected storage element.

US Patent:

20190004988, Jan 3, 2019

Filed:

Jun 28, 2017

Appl. No.:

15/635687

Inventors:

- San Jose CA, US
Randy Roberson - Lutz FL, US
Randall Hess - Colorado Springs CO, US
Michael Stillwell - Colorado Springs CO, US
Michael Walker - Colorado Springs CO, US

International Classification:

G06F 13/40
G06F 13/42
G06F 13/16
G06F 12/02

Abstract:

Described herein are enhancements for managing quality of service in a multi-host Peripheral Component Interconnect Express (PCIe) switching environment. In one implementation, a host system is configured to maintain quality of service statistics corresponding to data interactions with a PCIe storage device available via a PCIe switch. The host system may further receive secondary quality of service statistics for one or more other host systems communicatively coupled to the PCIe device via the PCIe switch, and determine a maximum queue depth for the host system based on the quality of service statistics and the second quality of service statistics to maintain a quality of service for the host systems.