Ravi R Subrahmanyan

US Patent:

6831925, Dec 14, 2004

Filed:

Apr 6, 1999

Appl. No.:

09/286927

Inventors:

Ravi Subrahmanyan - Windham NH
Mark L. Seiders - Mountain View CA
Peter R. Holloway - Andover MA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H04L 12413

US Classification:

370447, 370445

Abstract:

A structure and process are provided for using a single wire or data bus to detect collisions between two communication nodes connected by the single wire by sensing current changes in the wire, where large current changes indicate a collision. When a second node wants to obtain control of the wire on which a first node is transmitting data, the second node transmits a special data packet to ensure a collision and cause a large current to flow on the wire. Once a large current is detected in the wire to indicate a bit difference or collision, the first node stops transmitting and waits until it receives a synchronization bit pattern, which will indicate that the special data packet transmitted by the second node has ended. The two nodes are now synchronized, such that the second node has control of the wire and can begin transmission of a data packet. In order to indicate a collision, the large current flow must remain high after a specified time interval, such as a clock cycle.

US Patent:

6882662, Apr 19, 2005

Filed:

Jun 7, 2001

Appl. No.:

09/876297

Inventors:

Ravi Subrahmanyan - Windham NH, US
Jeffrey W. Spires - Plaistow NH, US

Assignee:

Applied Micro Circuits Corporation - Andover MA

International Classification:

H04L003/07

US Classification:

370506, 370516, 375372

Abstract:

An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signals embedded in the synchronized signal to determine a bit leak rate of bits from an elastic store following a pointer adjustment event such that the elastic store provides as an output a more-uniformly-distributed-gapped data stream.

US Patent:

6999480, Feb 14, 2006

Filed:

Nov 26, 2001

Appl. No.:

09/994460

Inventors:

Ravi Subrahmanyan - Windham NH, US
Anthony B. Candage - Andover MA, US

Assignee:

Applied Micro Circuits Corporation - Andover MA

International Classification:

H04L 12/28
H04L 25/64
H04J 3/07
H03L 7/06

US Classification:

370907, 370506, 370516, 370252, 327155, 327156, 375214, 375215, 375325

Abstract:

An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

US Patent:

7059248, Jun 13, 2006

Filed:

Oct 1, 2004

Appl. No.:

10/956416

Inventors:

Nandakumar Vaidyanathan - Huntington Beach CA, US
Ravi Subrahmanyan - Windham NH, US

International Classification:

B41M 1/42

US Classification:

101489, 101401, 347111, 347112

Abstract:

A print engine suitable for printing barcodes and other patterns using charged inks includes a semiconductor memory layer having memory circuits that are coupled to one or more line elements and/or printel cells. The printel cells and line elements either attract or do not attract charged ink based on the data stored in the corresponding memory circuit. The line elements and printel cells may be configured to form a linear barcode or a 2-dimensional barcode. The charged ink may also be electrically conducting and the line elements and printel cells may be configured to form electrical structures such as electrical circuits or antennae. The charged ink may also be electrically semiconducting and by the line elements and printel cells may be configured to form electronic semiconductor devices and circuits.

US Patent:

7121209, Oct 17, 2006

Filed:

Jan 16, 2004

Appl. No.:

10/759765

Inventors:

Nandakumar Vaidyanathan - Huntington Beach CA, US
Ravi Subrahmanyan - Windham NH, US

International Classification:

B41M 1/42

US Classification:

101489, 101401, 347111, 347112

Abstract:

The print engine is composed of a semiconductor memory layer overlaid on an insulated conductive layer with a one to one correspondence of each memory cell with the conductive pad on the insulated layer. The entire structure can be fashioned into a either a planar structure or a cylindrical structure with insulated conductive pads providing protection to the sensitive semiconductor memory from impact loading that occurs during the printing process.

US Patent:

7212599, May 1, 2007

Filed:

Jan 17, 2003

Appl. No.:

10/346550

Inventors:

Ravi Subrahmanyan - Windham NH, US
Jeffrey W. Spires - Plaistow NH, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H04L 7/00
H04L 25/00
H04L 25/40
H03D 3/24
H04J 3/06

US Classification:

375372, 375371, 375373, 370516

Abstract:

The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator. The digitally controlled read enable signal generator provides a read enable signal that is nominally the second data rate and that can be varied about the nominal second data rate in response to the control word.

US Patent:

7440533, Oct 21, 2008

Filed:

Jan 3, 2007

Appl. No.:

11/648920

Inventors:

Jeffrey W. Spires - Salt Lake City UT, US
Ravi Subrahmanyan - Windham NH, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H04L 25/00
H04J 3/07

US Classification:

375373, 370505

Abstract:

A system and modulation method are provided for reducing jitter in the mapping of information into Synchronous Payload Envelopes (SPEs), in a data tributary mapping system. The method comprises buffering data from a plurality of tributaries, and generating buffer-fill information responsive to the buffered data being written and read. The buffer-fill information is filtered, producing rate control information. The rate control information is modulated, and the modulated rate control information is used in controlling the mapping of buffered tributaries into a SPE. The rate control information can be modulated with periodic signals, such as a sine or square wave, and pseudorandom signals with an average value of about zero.

US Patent:

7457390, Nov 25, 2008

Filed:

Sep 29, 2006

Appl. No.:

11/541176

Inventors:

Jeffrey W. Spires - Salt Lake City UT, US
Ravi Subrahmanyan - Windham NH, US

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H04L 25/00

US Classification:

375372

Abstract:

A timeshared data tributary mapping system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries and stores current buffer-fill information at a rate of about one tributary per Fsys clock cycle. An accumulation of buffer-fill information for the plurality of tributaries is updated with current buffer-fill information every Fsys clock cycle. The accumulation of buffer-fill information for the plurality of tributaries is sampled at a sample rate frequency (Fsample), where Fsample