Ray R Abrishami

US Patent:

56442513, Jul 1, 1997

Filed:

Sep 26, 1995

Appl. No.:

8/533688

Inventors:

Michael Colwell - Livermore CA
Rochit Rajsuman - San Jose CA
Ray Abrishami - Los Altos CA
Zarir B. Sarkari - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 1900

US Classification:

326 16

Abstract:

An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

US Patent:

44712359, Sep 11, 1984

Filed:

May 3, 1982

Appl. No.:

6/374538

Inventors:

Shashi Sakhuja - Santa Clara CA
Ray Abrishami - Santa Clara CA

Assignee:

Data General Corporation - Westboro MA

International Classification:

H03K 526
H03K 1716

US Classification:

307234

Abstract:

A circuit is described for discriminating relatively wide, high level signal pulses from relatively narrow and/or low level noise pulses. The input pulses are first passed through a first Schmitt trigger to eliminate low level noise pulses. The output of the first Schmitt trigger is connected to a signal input of a "D" latch and to one input of an exclusive NOR gate. The exclusive NOR gate compares the input pulses from the output of the first Schmitt trigger with an output of the latch through a second Schmitt trigger. An R-C integrating network connected between the exclusive NOR gate and the second Schmitt trigger produces a rising input signal to the second Schmitt trigger that reaches the threshold level of the Schmitt trigger only for input signal pulses that exceed a given pulse width.

US Patent:

56708904, Sep 23, 1997

Filed:

Sep 26, 1995

Appl. No.:

8/533704

Inventors:

Michael Colwell - Livermore CA
Rochit Rajsuman - San Jose CA
Ray Abrishami - Los Altos CA
Zarir B. Sarkari - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R 3128

US Classification:

324765

Abstract:

An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.