Raymond J Balda

US Patent:

6489211, Dec 3, 2002

Filed:

Mar 1, 2000

Appl. No.:

09/516349

Inventors:

Raymond J. Balda - Tempe AZ
Robert A. Pryor - Mesa AZ
James D. Paulsen - Tempe AZ
Robert J. Johnsen - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 218238

US Classification:

438322, 438325, 438327

Abstract:

A method of manufacturing a semiconductor component includes providing a composite substrate ( ) with a dielectric portion and a semiconductor portion and growing an epitaxial layer ( ) over the composite substrate. The epitaxial layer has a polycrystalline portion ( ) over the dielectric portion of the composite substrate and also has a monocrystalline portion ( ) over the semiconductor portion of the composite substrate. A first dopant is diffused into the monocrystalline portion of the epitaxial layer to form an emitter region in the monocrystalline portion of the epitaxial layer while a second dopant is simultaneously diffused into the monocrystalline portion of the epitaxial layer to form an enhanced portion of the base region.

US Patent:

6900105, May 31, 2005

Filed:

Aug 2, 2002

Appl. No.:

10/211842

Inventors:

Raymond J. Balda - Tempe AZ, US
Robert A. Pryor - Mesa AZ, US
Joseph L. Petrucci, Jr. - Dresden, DE
Robert J. Johnsen - Scottsdale AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L021/331

US Classification:

438361, 438353, 438357, 438359, 438360, 438369

Abstract:

In a semiconductor manufacturing method, an emitter region () and a base enhancement region () are formed to provide linear voltage, capacitance and low resistance characteristics. In the manufacturing method, a semiconductor device () is formed on a silicon substrate layer () with an epitaxial layer (). Trenches () are cut into the epitaxial layer () and filled with oxide () to provide reduced junction capacitance and reduced base resistance. The emitter region () and the base enhancement region () are simultaneously formed through an anneal process.

US Patent:

50670026, Nov 19, 1991

Filed:

Jan 31, 1989

Appl. No.:

7/304984

Inventors:

Peter J. Zdebel - Mesa AZ
Raymond J. Balda - Tempe AZ
Bor-Yuan Hwang - Chandler AZ
Allen J. Wagner - Phoenix AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2904
H01L 2910
H01L 2702
H01L 2972

US Classification:

357 59

Abstract:

A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

US Patent:

48371769, Jun 6, 1989

Filed:

Jan 30, 1987

Appl. No.:

7/009322

Inventors:

Peter J. Zdebel - Mesa AZ
Raymond J. Balda - Tempe AZ
Bor-Yuan Hwang - Chandler AZ
Allen J. Wagner - Phoenix AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 21265

US Classification:

437 31

Abstract:

A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

US Patent:

45233721, Jun 18, 1985

Filed:

May 7, 1984

Appl. No.:

6/607868

Inventors:

Raymond J. Balda - Tempe AZ
Yefim Bukhman - Tempe AZ
Willis R. Goodner - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21312

US Classification:

29590

Abstract:

A process is disclosed for fabricating semiconductor devices, and especially for fabricating semiconductor devices having multiple levels of metallization separated by polyimide or other organic materials. The process avoids the sputter etching and redeposition of the lower metal layer during reactive ion etching of openings through the organic layer. Sequential layers overlying the first layer of metallization include a layer of oxide, a layer of organic material, and a second layer of oxide. The second layer of oxide functions as a hard mask for patterning the organic material. The first layer of oxide acts as an etch stop and protective layer to prevent attack of the underlying metal during reactive ion etching of the organic layer. The first layer of oxide is of limited areal extent to avoid subsequent problems with the organic layer. The oxide located at the bottom of the opening through the organic material as well as the second layer of oxide and any oxide which is sputtered and redeposited on the walls of the opening through the organic material are easily removed in a single etch step without adversely affecting the underlying metallization.

US Patent:

47404787, Apr 26, 1988

Filed:

Jan 30, 1987

Appl. No.:

7/008991

Inventors:

Peter J. Zdebel - Mesa AZ
Raymond J. Balda - Tempe AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 21265
H01L 21225

US Classification:

437 33

Abstract:

A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a four layer poly process which produces small device areas without relying upon restrictive photolithography tolerances. A master mask is used to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. A double implant doping process is used to control the Gummel number in the base of bipolar transistors and like regions. A shallow implant is placed in a screen oxide and a deep implant into the desired base location. The dopant saturated screen oxide prevents segregation of the deep base implant during subsequent heat treatment. The double implant process applies to many desired device structures.