Raymond C Yuen

US Patent:

41896718, Feb 19, 1980

Filed:

Apr 3, 1978

Appl. No.:

5/893207

Inventors:

Raymond C. Yuen - Poway CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G05F 500

US Classification:

323 19

Abstract:

A voltage regulator and regulator buffer having a plurality of matched transistors including an output transistor arranged such that the fluctuation in supply voltage is sensed by a shunt circuit which tracks such voltage fluctuation and eliminates such fluctuations from the output transistor by causing current variations due to supply voltage variations to flow through another transistor connected in parallel with the output transistor thus eliminating the first order effects of power supply voltage variations on output voltage. The voltage regulator buffer comprises a plurality of matched transistors which also has a voltage supply variation shunt circuit similar to the regulator shunt circuit to regulate the current through an output transistor thus eliminating the effect of the power supply voltage thereon and providing an output voltage of a precise amount.

US Patent:

41953584, Mar 25, 1980

Filed:

Dec 26, 1978

Appl. No.:

5/973175

Inventors:

Raymond C. Yuen - San Diego CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G11C 800
G11C 1700

US Classification:

365230

Abstract:

Circuitry for programming a read-only memory comprising a plurality of decoding transistors of low current density for selecting the row of the programmable matrix and which function to operate a high current density control transistor through a large voltage swing for controlling an output transistor of the circuitry connected directly to the array. The decoding transistors are operable through a CML voltage swing in a non-saturated mode with minimum current to operate the control transistor of high current density from cut-off to saturation to turn the output transistor ON or OFF which in turn directs the high voltage from a high voltage source to the programmable memory.

US Patent:

48749702, Oct 17, 1989

Filed:

May 11, 1988

Appl. No.:

7/193261

Inventors:

Bruce H. Coy - San Diego CA
Raymond C. Yuen - San Diego CA

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H03K 19092
H03K 19086

US Classification:

307475

Abstract:

The described embodiment of the present invention provides an output drive circuit having an input circuit comprising a differentially coupled pair of transistors. The output of the differentially paired transistors is provided to a pair of output driver transistors connected in a Darlington or a common collector-common emitter configuration which provides an output pull up signal to an output pin of the integrated circuit containing the described output driver. The opposite output of the differentially coupled pair is provided to a circuit which provides a pull down pulse to quickly shut off the transistor pair during the high to low transition of the output driver transistor. The use of the output driver transistor driver minimizes the current required by the differential pair and the fast pull down circuit eliminates the speed disadvantage of using a transistor pair output driver.

US Patent:

47514043, Jun 14, 1988

Filed:

Oct 31, 1986

Appl. No.:

6/926378

Inventors:

Raymond C. Yuen - San Diego CA

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H03K 301
H03K 326
H03K 19086

US Classification:

307297

Abstract:

In a multi-level ECL series gating circuit with three levels of gating which operates over specified operating circuit voltage and operating circuit temperature ranges, provision is made for stabilizing the magnitude of the circuit source current over the operating voltage and temperature ranges by regulating the bias voltage which determines the circuit source current. The bias voltage is regulated according to the inverse of the operating temperature to account for the temperature characteristics of the base-to-emitter diode in the transistor generating the circuit current. The magnitude of the bias voltage over the temperature range never reaches a level which will send the circuit current transistor into saturation at any circuit voltage in the operating range.

US Patent:

46270850, Dec 2, 1986

Filed:

Jun 29, 1984

Appl. No.:

6/626401

Inventors:

Raymond C. Yuen - San Diego CA

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

G11C 700
H03K 1726

US Classification:

377 81

Abstract:

A circuit for controlling flip-flop hold and set-scan operations responds to one state of a HOLD/PASS signal by blocking the provision of a flip-flop CLOCK signal to one or more flip-flops which are to conduct a holding operation. The circuit responds to the pass state of the HOLD/PASS signal by permitting the flip-flop clock to be provided to the control flip-flops so that they can conduct shift or pass operations.

US Patent:

47361255, Apr 5, 1988

Filed:

Aug 28, 1986

Appl. No.:

6/901138

Inventors:

Raymond C. Yuen - San Diego CA

Assignee:

Applied Micro Circuits Corporation - San Diego CA

International Classification:

H03K 19092
H03K 19003
H03K 1714
G05F 316

US Classification:

307475

Abstract:

A circuit for translating TTL-to-ECL-type signals utilizes an unbuffered emitter-coupled transistor pair for shifting signal levels. The emitter-coupled transistor pair operates by switching a current from a current-source transistor, with the switching being performed against a temperature-compensated threshold voltage that is derived from a reference voltage provided to the current source transistor. Direct, unbuffered switching of the emitter-coupled transistor pair insures rapid, symmetrical response to the TTL signals that drive the transistor pair and produces high-quality, relatively undistorted ECL waveforms. Provision of a current-source reference voltage stabilized with respect to temperature also contributes to reduction of distortion in the ECL waveforms. The threshold voltage is obtained from the current source reference voltage through a current mirror circuit.

US Patent:

41834607, Jan 15, 1980

Filed:

Dec 23, 1977

Appl. No.:

5/863696

Inventors:

Raymond C. Yuen - Poway CA
Mark A. Menezes - Rancho Bernardo CA
Herbert Stopper - Orchard Lake MI

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

G01R 3128
G06F 1100

US Classification:

235302

Abstract:

An In-Situ Test and Diagnostic Circuit and Method to monitor the integrity of external connections of a current mode logic integrated circuit chip (inputs and outputs) as well as the integrity of the logic function thereof. The circuit comprises three parts: an "Open" Input Detector to detect open connections or connections that are becoming open between one chip and another; an Output Short Detector to monitor shorts at any chip output; and a Signature Test and Diagnostic circuit to determine if the logic function of the chip itself is operational. All the foregoing circuit parts are formed as an integral part of each CML chip and connected to an output terminal called a Test and Diagnostic Pin.

US Patent:

41525418, May 1, 1979

Filed:

Feb 3, 1978

Appl. No.:

5/874866

Inventors:

Raymond C. Yuen - Poway CA

Assignee:

Burroughs Corporation - Detroit MI

International Classification:

H04L 514

US Classification:

178 59

Abstract:

A duplex driver/receiver module having circuitry which permits the sending and receiving of data from an identical module simultaneously, utilizing resistive and gating techniques to overcome differential noise, to accommodate circuit manufacture process variations and transmission line resistances within the CML logic environment.